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@@ -19,31 +19,28 @@ The UTCB stores message registers that are transferred between threads during an
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.BR l4_ipc ()
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system call reference page.
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UTCB may also be used for any thread-local information that is private to each thread in an address space. For example on stacked IPCs where a new IPC is initiated before the current IPC has been completed,
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.I saved_tag
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and
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.I saved_sender
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fields serve the purpose of saving the unfinished IPC information.
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.I notify
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field provides asynchronous notification slots for asynchronous messages. For a full description of each field please refer to below.
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.RI "UTCB may also be used for any thread-local information that is private to each thread in an address space. For example on stacked IPCs where a new IPC is initiated before the current IPC has been completed, " "saved_tag " "and " "saved_sender " "fields serve the purpose of saving the unfinished IPC information. For a full description of each field please refer to below. "
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.fi
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.ti 8
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.BI "struct " "utcb "
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{
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.ti 12
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.ti 16
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.BI "u32 " "mr[MR_TOTAL]" "; /* MRs that are mapped to real registers */"
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.ti 12
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.ti 16
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.BI "u32 " "saved_tag" "; /* Saved tag field for stacked ipc */"
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.ti 12
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.ti 16
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.BI "u32 " "saved_sender" "; /* Saved sender field for stacked ipc */"
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.ti 12
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.BI "u8 " " notify[8]" "; /* Asynchronous notification slots. One slot per byte. */"
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.ti 12
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.ti 16
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.BI "u32 " "mr_rest[MR_REST]" "; /* Complete the utcb to 64 words */"
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.ti 8
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};
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.TP
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.fi
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.I mr[MR_TOTAL]
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.RB "Primary message registers. On the ARM Architecture there are 6 of these registers, named as " "MR0 - MR5" ". As an optimisation, these registers may be mapped to real registers by the kernel during an ipc. However this behaviour is not warranted by the kernel API."
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.TP
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.fi
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.I saved_tag
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@@ -54,10 +51,8 @@ Saved IPC tag field on a stacked IPC.
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Saved sender id on a stacked IPC.
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.TP
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.fi
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.I notify
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This field consists of eight single-byte slots that are used for asynchronous messaging. Each thread subscribes to one or more slots, and may sleep on these slots if needed. Any asynchronous message sent to the thread updates these slots with new values. IRQs are often handled in userspace with the help of these slots. See
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.B l4_irq_control()
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for detailed information.
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.I mr_rest[MR_REST]
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.RB "Rest of the message registers located on the UTCB. These registers are transferred upon an ipc only if the ipc type is a " "full ipc" ". See " "l4_ipc" "(7) for more details."
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.SH UTCB ALLOCATION
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UTCB address and memory allocation is not maintained by Codezero Microkernel. Both UTCB allocation and maintainence is expected to be handled in userspace.
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@@ -70,20 +65,20 @@ The simplest solution to create a UTCB is to simply declare a UTCB size aligned
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.BI "#define DECLARE_UTCB(" name ")
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.B struct utcb name ALIGN(sizeof(struct utcb))
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and use it by:
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.B DECLARE_UTCB(utcb);
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While this works, it requires the statically allocated structure to lie in a virtual address area that is disjoint from any other virtual address in the system.
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Pagers may set a thread's utcb by the
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.I l4_exchange_registers()
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system call. See this call on how to set up a new utcb.
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.RB "Pagers may set a thread's utcb by the " "l4_exchange_registers() " "system call. Please see " "l4_exchange_registers" "(7) for more details."
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.fi
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The UTCB structure may be of variable size, and has been set to a total of 256 bytes on an ARM system. The UTCB structure is subject to change. New fields may be reserved on the UTCB as needed.
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.in 8
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.SH L4 Userspace Library Functions
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.SH L4 USERSPACE LIBRARY
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.nf
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/* Functions to read/write utcb registers */
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@@ -91,4 +86,4 @@ The UTCB structure may be of variable size, and has been set to a total of 256 b
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.BI "static inline void write_mr(unsigned int " "offset" ", unsigned int " "val" ")"
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.SH SEE ALSO
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.BR "l4_irq_control"(7), " l4_exchange_registers"(7)
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.BR "l4_ipc"(7), " l4_exchange_registers"(7)
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Bahadir Balban