mirror of
https://github.com/drasko/codezero.git
synced 2026-01-21 15:23:15 +01:00
Kernel updates since December 2009
This commit is contained in:
Bahadir Balban
15
conts/libdev/uart/omap/SConscript
Normal file
15
conts/libdev/uart/omap/SConscript
Normal file
@@ -0,0 +1,15 @@
|
||||
Import('env', 'platform')
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#Platforms using omap_uart
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plat_list = 'beagle'
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# The set of source files associated with this SConscript file.
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src_local = []
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#for plat_supported in plat_list:
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#if plat_supported == platform:
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if plat_list == platform:
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src_local += ['uart.c']
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obj = env.StaticObject(src_local)
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Return('obj')
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115
conts/libdev/uart/omap/uart.c
Normal file
115
conts/libdev/uart/omap/uart.c
Normal file
@@ -0,0 +1,115 @@
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/*
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* UART driver used by OMAP devices
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#include <libdev/uart.h>
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#include <libdev/io.h>
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#include "uart.h"
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#define OMAP_UART_TXFE 0x20
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void uart_tx_char(unsigned long uart_base, char c)
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{
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volatile u32 reg;
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/* Check if there is space for tx */
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do {
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reg = read(uart_base + OMAP_UART_LSR);
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} while(!(reg & OMAP_UART_TXFE));
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write(c, uart_base + OMAP_UART_THR);
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}
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#define OMAP_UART_RXFNE 0x1
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#define OMAP_UART_RX_FIFO_STATUS 0x8
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char uart_rx_char(unsigned long uart_base)
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{
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volatile u32 reg;
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/* Check if pending data is there */
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do {
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reg = read(uart_base + OMAP_UART_LSR);
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} while(!(reg & OMAP_UART_RXFNE));
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#if 0
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/* Check if there is some error in recieve */
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if(reg & OMAP_UART_RX_FIFO_STATUS)
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return -1;
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#endif
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return (char)read(uart_base + OMAP_UART_RHR);
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}
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void uart_set_baudrate(unsigned long uart_base, u32 baudrate)
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{
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u32 clk_div;
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/* 48Mhz clock fixed on beagleboard */
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const u32 clkrate = 48000000;
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/* If baud out of range, set default rate */
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if(baudrate > 3686400 || baudrate < 300)
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baudrate = 115200;
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clk_div = clkrate/(16 * baudrate);
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/* Set clockrate in DLH and DLL */
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write((clk_div & 0xff), uart_base + OMAP_UART_DLL);
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write(((clk_div >> 8) & 0xff ), uart_base + OMAP_UART_DLH);
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}
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void uart_init(unsigned long uart_base)
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{
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/* Disable UART */
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uart_select_mode(uart_base, OMAP_UART_MODE_DEFAULT);
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/* Disable interrupts */
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uart_disable_interrupt(uart_base);
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/* Change to config mode, to set baud divisor */
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uart_set_link_control(uart_base, OMAP_UART_BANKED_MODE_CONFIG_A);
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/* Set the baud rate */
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uart_set_baudrate(uart_base, 115200);
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/* Switch to operational mode */
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uart_set_link_control(uart_base, OMAP_UART_BANKED_MODE_OPERATIONAL);
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/* Set up the link- parity, data bits stop bits to 8N1 */
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uart_disable_parity(uart_base);
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uart_set_data_bits(uart_base, OMAP_UART_DATA_BITS_8);
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uart_set_stop_bits(uart_base, OMAP_UART_STOP_BITS_1);
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/* Disable Fifos */
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uart_disable_fifo(uart_base);
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/* Enable modem Rx/Tx */
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uart_enable_tx(uart_base);
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uart_enable_rx(uart_base);
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/* Enable UART in 16x mode */
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uart_select_mode(uart_base, OMAP_UART_MODE_UART16X);
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}
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unsigned long uart_print_base;
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void platform_init(void)
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{
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uart_print_base = OMAP_UART_BASE;
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/*
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* We dont need to initialize uart here for variant-userspace,
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* as this is the same uart as used by kernel and hence
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* already initialized, we just need
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* a uart struct instance with proper base address.
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*
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* But in case of baremetal like loader, no one has done
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* initialization, so we need to do it.
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*/
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#if defined(VARIANT_BAREMETAL)
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uart_init(uart_print_base);
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#endif
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}
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195
conts/libdev/uart/omap/uart.h
Normal file
195
conts/libdev/uart/omap/uart.h
Normal file
@@ -0,0 +1,195 @@
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/*
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* OMAP UART Generic driver implementation.
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*
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* Copyright (C) 2007 Bahadir Balban
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*
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* The particular intention of this code is that it has been carefully written
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* as decoupled from os-specific code and in a verbose way such that it clearly
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* demonstrates how the device operates, reducing the amount of time to be spent
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* for understanding the operational model and implementing a driver from
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* scratch. This is the very first to be such a driver so far, hopefully it will
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* turn out to be useful.
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*/
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#ifndef __OMAP_UART_H__
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#define __OMAP_UART_H__
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#include <l4/config.h> /* To get PLATFORM */
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#include <l4lib/types.h>
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#if defined(VARIANT_USERSPACE)
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/* FIXME: Take this value in agreement from kernel, or from kernel only */
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#include <l4/macros.h>
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#include INC_ARCH(io.h)
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#define OMAP_UART_BASE USERSPACE_CONSOLE_VBASE
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#endif
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#if defined(VARIANT_BAREMETAL)
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#if defined(CONFIG_PLATFORM_BEAGLE)
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#define OMAP_UART_BASE 0x49020000
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#endif
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#endif
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/* Register offsets */
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#define OMAP_UART_DLL 0x00
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#define OMAP_UART_THR 0x00
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#define OMAP_UART_RHR 0x00
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#define OMAP_UART_DLH 0x04
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#define OMAP_UART_IER 0x04
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#define OMAP_UART_FCR 0x08
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#define OMAP_UART_MCR 0x10
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#define OMAP_UART_LSR 0x14
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#define OMAP_UART_MDR1 0x20
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#define OMAP_UART_LCR 0x0C
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/* Modes supported by OMAP UART/IRDA/CIR IP */
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#define OMAP_UART_MODE_UART16X 0x0
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#define OMAP_UART_MODE_SIR 0x1
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#define OMAP_UART_MODE_UART16X_AUTO_BAUD 0x2
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#define OMAP_UART_MODE_UART13X 0x3
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#define OMAP_UART_MODE_MIR 0x4
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#define OMAP_UART_MODE_FIR 0x5
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#define OMAP_UART_MODE_CIR 0x6
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#define OMAP_UART_MODE_DEFAULT 0x7 /* Disable */
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/* Number of data bits for UART */
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#define OMAP_UART_DATA_BITS_5 0x0
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#define OMAP_UART_DATA_BITS_6 0x1
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#define OMAP_UART_DATA_BITS_7 0x2
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#define OMAP_UART_DATA_BITS_8 0x3
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/* Stop bits to be used for UART data */
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#define OMAP_UART_STOP_BITS_1 0x0
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#define OMAP_UART_STOP_BITS_1_5 0x1
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/* Banked Register modes- ConfigA, ConfigB, Operational */
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#define OMAP_UART_BANKED_MODE_OPERATIONAL 0x00
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#define OMAP_UART_BANKED_MODE_CONFIG_A 0x80
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#define OMAP_UART_BANKED_MODE_CONFIG_B 0xBF
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void uart_tx_char(unsigned long uart_base, char c);
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char uart_rx_char(unsigned long uart_base);
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void uart_set_baudrate(unsigned long uart_base, u32 baudrate);
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void uart_init(unsigned long uart_base);
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#define OMAP_UART_FIFO_ENABLE (1 << 0)
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#define OMAP_UART_RX_FIFO_CLR (1 << 1)
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#define OMAP_UART_TX_FIFO_CLR (1 << 2)
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static inline void uart_enable_fifo(unsigned long uart_base)
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{
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volatile u32 reg = read(uart_base + OMAP_UART_FCR);
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reg |= (OMAP_UART_FIFO_ENABLE | OMAP_UART_RX_FIFO_CLR |
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OMAP_UART_TX_FIFO_CLR);
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write(reg, uart_base + OMAP_UART_FCR);
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}
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static inline void uart_disable_fifo(unsigned long uart_base)
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{
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volatile u32 reg= read(uart_base + OMAP_UART_FCR);
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reg &= (~OMAP_UART_FIFO_ENABLE | OMAP_UART_RX_FIFO_CLR |
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OMAP_UART_TX_FIFO_CLR);
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write(reg, uart_base + OMAP_UART_FCR);
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}
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#define OMAP_UART_TX_ENABLE (1 << 0)
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static inline void uart_enable_tx(unsigned long uart_base)
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{
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volatile u32 reg = read(uart_base + OMAP_UART_MCR);
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reg |= OMAP_UART_TX_ENABLE;
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write(reg, uart_base + OMAP_UART_MCR);
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}
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static inline void uart_disable_tx(unsigned long uart_base)
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{
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volatile u32 reg = read(uart_base + OMAP_UART_MCR);
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reg &= ~OMAP_UART_TX_ENABLE;
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write(reg, uart_base + OMAP_UART_MCR);
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}
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#define OMAP_UART_RX_ENABLE (1 << 1)
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static inline void uart_enable_rx(unsigned long uart_base)
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{
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volatile u32 reg = read(uart_base + OMAP_UART_MCR);
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reg |= OMAP_UART_RX_ENABLE;
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write(reg, uart_base + OMAP_UART_MCR);
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}
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static inline void uart_disable_rx(unsigned long uart_base)
|
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{
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volatile u32 reg = read(uart_base + OMAP_UART_MCR);
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reg &= ~OMAP_UART_RX_ENABLE;
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write(reg, uart_base + OMAP_UART_MCR);
|
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}
|
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||||
#define OMAP_UART_STOP_BITS_MASK (1 << 2)
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static inline void uart_set_stop_bits(unsigned long uart_base, int bits)
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||||
{
|
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volatile u32 reg = read(uart_base + OMAP_UART_LCR);
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reg &= ~OMAP_UART_STOP_BITS_MASK;
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||||
reg |= (bits << 2);
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||||
write(reg, uart_base + OMAP_UART_LCR);
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}
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|
||||
#define OMAP_UART_DATA_BITS_MASK (0x3)
|
||||
static inline void uart_set_data_bits(unsigned long uart_base, int bits)
|
||||
{
|
||||
volatile u32 reg = read(uart_base + OMAP_UART_LCR);
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reg &= ~OMAP_UART_DATA_BITS_MASK;
|
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reg |= bits;
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||||
write(reg, uart_base + OMAP_UART_LCR);
|
||||
}
|
||||
|
||||
#define OMAP_UART_PARITY_ENABLE (1 << 3)
|
||||
static inline void uart_enable_parity(unsigned long uart_base)
|
||||
{
|
||||
volatile u32 reg = read(uart_base + OMAP_UART_LCR);
|
||||
reg |= OMAP_UART_PARITY_ENABLE;
|
||||
write(reg, uart_base + OMAP_UART_LCR);
|
||||
}
|
||||
|
||||
static inline void uart_disable_parity(unsigned long uart_base)
|
||||
{
|
||||
volatile u32 reg = read(uart_base + OMAP_UART_LCR);
|
||||
reg &= ~OMAP_UART_PARITY_ENABLE;
|
||||
write(reg, uart_base + OMAP_UART_LCR);
|
||||
}
|
||||
|
||||
#define OMAP_UART_PARITY_EVEN (1 << 4)
|
||||
static inline void uart_set_even_parity(unsigned long uart_base)
|
||||
{
|
||||
volatile u32 reg = read(uart_base + OMAP_UART_LCR);
|
||||
reg |= OMAP_UART_PARITY_EVEN;
|
||||
write(reg, uart_base + OMAP_UART_LCR);
|
||||
}
|
||||
|
||||
static inline void uart_set_odd_parity(unsigned long uart_base)
|
||||
{
|
||||
volatile u32 reg = read(uart_base + OMAP_UART_LCR);
|
||||
reg &= ~OMAP_UART_PARITY_EVEN;
|
||||
write(reg, uart_base + OMAP_UART_LCR);
|
||||
}
|
||||
|
||||
static inline void uart_select_mode(unsigned long uart_base, int mode)
|
||||
{
|
||||
write(mode, uart_base + OMAP_UART_MDR1);
|
||||
}
|
||||
|
||||
#define OMAP_UART_INTR_EN 1
|
||||
static inline void uart_enable_interrupt(unsigned long uart_base)
|
||||
{
|
||||
write(OMAP_UART_INTR_EN, uart_base + OMAP_UART_IER);
|
||||
}
|
||||
|
||||
static inline void uart_disable_interrupt(unsigned long uart_base)
|
||||
{
|
||||
write((~OMAP_UART_INTR_EN), uart_base + OMAP_UART_IER);
|
||||
}
|
||||
|
||||
static inline void uart_set_link_control(unsigned long uart_base, int mode)
|
||||
{
|
||||
write(mode, uart_base + OMAP_UART_LCR);
|
||||
}
|
||||
|
||||
#endif /* __OMAP_UART_H__ */
|
||||
14
conts/libdev/uart/pl011/SConscript
Normal file
14
conts/libdev/uart/pl011/SConscript
Normal file
@@ -0,0 +1,14 @@
|
||||
Import('env', 'platform')
|
||||
|
||||
#Platforms using pl011
|
||||
plat_list = ('eb', 'pba8', 'pba9', 'pb11mpcore', 'pb926')
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src_local = []
|
||||
|
||||
for plat_supported in plat_list:
|
||||
if plat_supported == platform:
|
||||
src_local += Glob('*.c')
|
||||
|
||||
obj = env.StaticObject(src_local)
|
||||
Return('obj')
|
||||
127
conts/libdev/uart/pl011/uart.c
Normal file
127
conts/libdev/uart/pl011/uart.c
Normal file
@@ -0,0 +1,127 @@
|
||||
/*
|
||||
* PL011 UART driver
|
||||
*
|
||||
* Copyright (C) 2009 B Labs Ltd.
|
||||
*/
|
||||
#include <libdev/uart.h>
|
||||
#include <libdev/io.h>
|
||||
#include "uart.h"
|
||||
|
||||
/* Error status bits in receive status register */
|
||||
#define PL011_FE (1 << 0)
|
||||
#define PL011_PE (1 << 1)
|
||||
#define PL011_BE (1 << 2)
|
||||
#define PL011_OE (1 << 3)
|
||||
|
||||
/* Status bits in flag register */
|
||||
#define PL011_TXFE (1 << 7)
|
||||
#define PL011_RXFF (1 << 6)
|
||||
#define PL011_TXFF (1 << 5)
|
||||
#define PL011_RXFE (1 << 4)
|
||||
#define PL011_BUSY (1 << 3)
|
||||
#define PL011_DCD (1 << 2)
|
||||
#define PL011_DSR (1 << 1)
|
||||
#define PL011_CTS (1 << 0)
|
||||
|
||||
void uart_tx_char(unsigned long base, char c)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
do {
|
||||
val = read((base + PL011_UARTFR));
|
||||
} while (val & PL011_TXFF); /* TX FIFO FULL */
|
||||
|
||||
write(c, (base + PL011_UARTDR));
|
||||
}
|
||||
|
||||
char uart_rx_char(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
do {
|
||||
val = read(base + PL011_UARTFR);
|
||||
} while (val & PL011_RXFE); /* RX FIFO Empty */
|
||||
|
||||
return (char)read((base + PL011_UARTDR));
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the baud rate in kbps. It is recommended to use
|
||||
* standard rates such as: 1200, 2400, 3600, 4800, 7200,
|
||||
* 9600, 14400, 19200, 28800, 38400, 57600 76800, 115200.
|
||||
*/
|
||||
void pl011_set_baudrate(unsigned long base, unsigned int baud,
|
||||
unsigned int clkrate)
|
||||
{
|
||||
const unsigned int uartclk = 24000000; /* 24Mhz clock fixed on pb926 */
|
||||
unsigned int val = 0, ipart = 0, fpart = 0;
|
||||
|
||||
/* Use default pb926 rate if no rate is supplied */
|
||||
if (clkrate == 0)
|
||||
clkrate = uartclk;
|
||||
if (baud > 115200 || baud < 1200)
|
||||
baud = 38400; /* Default rate. */
|
||||
|
||||
/* 24000000 / (38400 * 16) */
|
||||
ipart = 39;
|
||||
|
||||
write(ipart, base + PL011_UARTIBRD);
|
||||
write(fpart, base + PL011_UARTFBRD);
|
||||
|
||||
/*
|
||||
* For the IBAUD and FBAUD to update, we need to
|
||||
* write to UARTLCR_H because the 3 registers are
|
||||
* actually part of a single register in hardware
|
||||
* which only updates by a write to UARTLCR_H
|
||||
*/
|
||||
val = read(base + PL011_UARTLCR_H);
|
||||
write(val, base + PL011_UARTLCR_H);
|
||||
|
||||
}
|
||||
|
||||
void uart_init(unsigned long uart_base)
|
||||
{
|
||||
/* Initialise data register for 8 bit data read/writes */
|
||||
pl011_set_word_width(uart_base, 8);
|
||||
|
||||
/*
|
||||
* Fifos are disabled because by default it is assumed the port
|
||||
* will be used as a user terminal, and in that case the typed
|
||||
* characters will only show up when fifos are flushed, rather than
|
||||
* when each character is typed. We avoid this by not using fifos.
|
||||
*/
|
||||
pl011_disable_fifos(uart_base);
|
||||
|
||||
/* Set default baud rate of 38400 */
|
||||
pl011_set_baudrate(uart_base, 38400, 24000000);
|
||||
|
||||
/* Set default settings of 1 stop bit, no parity, no hw flow ctrl */
|
||||
pl011_set_stopbits(uart_base, 1);
|
||||
pl011_parity_disable(uart_base);
|
||||
|
||||
/* Enable rx, tx, and uart chip */
|
||||
pl011_tx_enable(uart_base);
|
||||
pl011_rx_enable(uart_base);
|
||||
pl011_uart_enable(uart_base);
|
||||
}
|
||||
|
||||
unsigned long uart_print_base;
|
||||
|
||||
void platform_init(void)
|
||||
{
|
||||
uart_print_base = PL011_BASE;
|
||||
|
||||
/*
|
||||
* We dont need to initialize uart here for variant-userspace,
|
||||
* as this is the same uart as used by kernel and hence
|
||||
* already initialized, we just need
|
||||
* a uart struct instance with proper base address.
|
||||
*
|
||||
* But in case of baremetal like loader, no one has done
|
||||
* initialization, so we need to do it.
|
||||
*/
|
||||
#if defined(VARIANT_BAREMETAL)
|
||||
uart_init(uart_print_base);
|
||||
#endif
|
||||
}
|
||||
|
||||
252
conts/libdev/uart/pl011/uart.h
Normal file
252
conts/libdev/uart/pl011/uart.h
Normal file
@@ -0,0 +1,252 @@
|
||||
/*
|
||||
* PL011 UART Generic driver implementation.
|
||||
* Copyright Bahadir Balban (C) 2009
|
||||
*/
|
||||
#ifndef __PL011_H__
|
||||
#define __PL011_H__
|
||||
|
||||
#include <l4/config.h> /* To get PLATFORM */
|
||||
#include <libdev/io.h>
|
||||
|
||||
#if defined(VARIANT_USERSPACE)
|
||||
/* FIXME: Take this value in agreement from kernel, or from kernel only */
|
||||
#include <l4/macros.h>
|
||||
#include INC_ARCH(io.h)
|
||||
#define PL011_BASE USERSPACE_CONSOLE_VBASE
|
||||
#endif
|
||||
|
||||
#if defined(VARIANT_BAREMETAL)
|
||||
#if defined(CONFIG_PLATFORM_PB926)
|
||||
#define PL011_BASE 0x101F1000
|
||||
#elif defined(CONFIG_PLATFORM_EB) || defined(CONFIG_PLATFORM_PB11MPCORE)
|
||||
#define PL011_BASE 0x10009000
|
||||
#elif defined(CONFIG_PLATFORM_PBA9) || defined(CONFIG_PLATFORM_PBA8)
|
||||
#define PL011_BASE 0x10009000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Register offsets */
|
||||
#define PL011_UARTDR 0x00
|
||||
#define PL011_UARTRSR 0x04
|
||||
#define PL011_UARTECR 0x04
|
||||
#define PL011_UARTFR 0x18
|
||||
#define PL011_UARTILPR 0x20
|
||||
#define PL011_UARTIBRD 0x24
|
||||
#define PL011_UARTFBRD 0x28
|
||||
#define PL011_UARTLCR_H 0x2C
|
||||
#define PL011_UARTCR 0x30
|
||||
#define PL011_UARTIFLS 0x34
|
||||
#define PL011_UARTIMSC 0x38
|
||||
#define PL011_UARTRIS 0x3C
|
||||
#define PL011_UARTMIS 0x40
|
||||
#define PL011_UARTICR 0x44
|
||||
#define PL011_UARTDMACR 0x48
|
||||
|
||||
/* IRQ bits for each uart irq event */
|
||||
#define PL011_RXIRQ (1 << 4)
|
||||
#define PL011_TXIRQ (1 << 5)
|
||||
#define PL011_RXTIMEOUTIRQ (1 << 6)
|
||||
#define PL011_FEIRQ (1 << 7)
|
||||
#define PL011_PEIRQ (1 << 8)
|
||||
#define PL011_BEIRQ (1 << 9)
|
||||
#define PL011_OEIRQ (1 << 10)
|
||||
|
||||
|
||||
void pl011_set_baudrate(unsigned long base, unsigned int baud,
|
||||
unsigned int clkrate);
|
||||
|
||||
#define PL011_UARTEN (1 << 0)
|
||||
static inline void pl011_uart_enable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTCR));
|
||||
val |= PL011_UARTEN;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_uart_disable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTCR));
|
||||
val &= ~PL011_UARTEN;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_TXE (1 << 8)
|
||||
static inline void pl011_tx_enable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTCR));
|
||||
val |= PL011_TXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_tx_disable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val =read((base + PL011_UARTCR));
|
||||
val &= ~PL011_TXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_RXE (1 << 9)
|
||||
static inline void pl011_rx_enable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTCR));
|
||||
val |= PL011_RXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_rx_disable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTCR));
|
||||
val &= ~PL011_RXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
|
||||
static inline void pl011_set_stopbits(unsigned long base, int stopbits)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
|
||||
if(stopbits == 2) { /* Set to two bits */
|
||||
val |= PL011_TWO_STOPBITS_SELECT;
|
||||
} else { /* Default is 1 */
|
||||
val &= ~PL011_TWO_STOPBITS_SELECT;
|
||||
}
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_PARITY_ENABLE (1 << 1)
|
||||
static inline void pl011_parity_enable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base +PL011_UARTLCR_H));
|
||||
val |= PL011_PARITY_ENABLE;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_parity_disable(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
val &= ~PL011_PARITY_ENABLE;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_PARITY_EVEN (1 << 2)
|
||||
static inline void pl011_set_parity_even(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
val |= PL011_PARITY_EVEN;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_set_parity_odd(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
val &= ~PL011_PARITY_EVEN;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_ENABLE_FIFOS (1 << 4)
|
||||
static inline void pl011_enable_fifos(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
val |= PL011_ENABLE_FIFOS;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_disable_fifos(unsigned long base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
val &= ~PL011_ENABLE_FIFOS;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
/* Sets the transfer word width for the data register. */
|
||||
static inline void pl011_set_word_width(unsigned long base, int size)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
if(size < 5 || size > 8) /* Default is 8 */
|
||||
size = 8;
|
||||
|
||||
/* Clear size field */
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
val &= ~(0x3 << 5);
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
|
||||
/*
|
||||
* The formula is to write 5 less of size given:
|
||||
* 11 = 8 bits
|
||||
* 10 = 7 bits
|
||||
* 01 = 6 bits
|
||||
* 00 = 5 bits
|
||||
*/
|
||||
val = read((base + PL011_UARTLCR_H));
|
||||
val |= (size - 5) << 5;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Defines at which level of fifo fullness an irq will be generated.
|
||||
* @xfer: tx fifo = 0, rx fifo = 1
|
||||
* @level: Generate irq if:
|
||||
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
|
||||
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
|
||||
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
|
||||
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
|
||||
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
|
||||
* 5-7 reserved reserved
|
||||
*/
|
||||
static inline void pl011_set_irq_fifolevel(unsigned long base, \
|
||||
unsigned int xfer, unsigned int level)
|
||||
{
|
||||
if(xfer != 1 && xfer != 0) /* Invalid fifo */
|
||||
return;
|
||||
if(level > 4) /* Invalid level */
|
||||
return;
|
||||
|
||||
write(level << (xfer * 3), (base + PL011_UARTIFLS));
|
||||
return;
|
||||
}
|
||||
|
||||
#endif /* __PL011__UART__ */
|
||||
|
||||
Reference in New Issue
Block a user