sambuc/codezero
1
0
Fork 0
mirror of https://github.com/drasko/codezero.git synced 2026-01-23 00:03:15 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

Patch for comments by bahadir

Browse Source
This commit is contained in:
Amit Mahajan
2009-11-01 00:51:55 +05:30
parent 52d346af40
commit 8d9f5f82d0
30 changed files with 105 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
include/l4/drivers/irq/gic/gic.h
View File

@@ -11,25 +11,25 @@
#include INC_PLAT(platform.h)
/* GIC CPU register offsets */
#define ARM_GIC_CPU_ICR 0x00 /* Interface Control */
#define ARM_GIC_CPUPMR 0x04 /* Interrupt Priority Mask */
#define ARM_GIC_CPU_BPR 0x08 /* Binary Point */
#define ARM_GIC_CPU_IAR 0x0c /* Interrupt Acknowledge */
#define ARM_GIC_CPU_EOIR 0x10 /* End of Interrupt */
#define ARM_GIC_CPU_RRI 0x14 /* Running Priority */
#define ARM_GIC_CPU_HPIR 0x18 /* Highest Priority Interrupt*/
#define ARM_GIC_CPU_IC 0x00 /* Interface Control */
#define ARM_GIC_CPUPM 0x04 /* Interrupt Priority Mask */
#define ARM_GIC_CPU_BP 0x08 /* Binary Point */
#define ARM_GIC_CPU_IA 0x0c /* Interrupt Acknowledge */
#define ARM_GIC_CPU_EOI 0x10 /* End of Interrupt */
#define ARM_GIC_CPU_RPI 0x14 /* Running Priority */
#define ARM_GIC_CPU_HPI 0x18 /* Highest Priority Interrupt*/
/* Distributor register map */
#define ARM_GIC_DIST_CR 0x000 /* Control Register */
#define ARM_GIC_DIST_ICTR 0x004 /* Interface Controller Type */
#define ARM_GIC_DIST_ISER 0x100 /* Interrupt Set Enable */
#define ARM_GIC_DIST_ICER 0x180 /* Interrupt Clear Enable */
#define ARM_GIC_DIST_ISPR 0x200 /* Interrupt Set Pending */
#define ARM_GIC_DIST_ICPR 0x280 /* Interrupt Clear Pending*/
#define ARM_GIC_DIST_ABR 0x300 /* Active Bit */
#define ARM_GIC_DIST_IPR 0x400 /* Interrupt Priority */
#define ARM_GIC_DIST_IPTR 0x800 /* Interrupt Processor Target */
#define ARM_GIC_DIST_ICR 0xc00 /* Interrupt Configuration */
#define ARM_GIC_DIST_SGIR 0xf00 /* Software Generated Interrupt */
#define ARM_GIC_DIST_CNTRL 0x000 /* Control Register */
#define ARM_GIC_DIST_ICT 0x004 /* Interface Controller Type */
#define ARM_GIC_DIST_ISE 0x100 /* Interrupt Set Enable */
#define ARM_GIC_DIST_ICE 0x180 /* Interrupt Clear Enable */
#define ARM_GIC_DIST_ISP 0x200 /* Interrupt Set Pending */
#define ARM_GIC_DIST_ICP 0x280 /* Interrupt Clear Pending*/
#define ARM_GIC_DIST_AB 0x300 /* Active Bit */
#define ARM_GIC_DIST_IP 0x400 /* Interrupt Priority */
#define ARM_GIC_DIST_IPT 0x800 /* Interrupt Processor Target */
#define ARM_GIC_DIST_IC 0xc00 /* Interrupt Configuration */
#define ARM_GIC_DIST_SGI 0xf00 /* Software Generated Interrupt */
#endif /* __ARM_GIC_H__ */