mirror of
https://github.com/drasko/codezero.git
synced 2026-01-12 02:43:15 +01:00
Added example cml2 configuration with 2 posix containers
This commit is contained in:
475
config/cml/examples/posix/cml2_oldconfig.in-2_posix_containers
Normal file
475
config/cml/examples/posix/cml2_oldconfig.in-2_posix_containers
Normal file
@@ -0,0 +1,475 @@
|
||||
#
|
||||
# Automatically generated, don't edit
|
||||
#
|
||||
# Generated on: bahadir-laptop
|
||||
# At: Sun, 18 Oct 2009 13:02:07 +0000
|
||||
# Linux version 2.6.24-22-generic (buildd@vernadsky) (gcc version 4.2.3 (Ubuntu 4.2.3-2ubuntu7)) #1 SMP Mon Nov 24 18:32:42 UTC 2008
|
||||
|
||||
#
|
||||
# Codezero Microkernel Configurator
|
||||
#
|
||||
|
||||
#
|
||||
# Main architecture
|
||||
#
|
||||
CONFIG_ARCH_ARM=y
|
||||
|
||||
|
||||
#
|
||||
# ARM Architecture Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# ARM Architecture Family
|
||||
#
|
||||
CONFIG_SUBARCH_V5=y
|
||||
CONFIG_SUBARCH_V6=n
|
||||
CONFIG_SUBARCH_V7=n
|
||||
|
||||
|
||||
#
|
||||
# ARM CPU type
|
||||
#
|
||||
|
||||
#
|
||||
# ARM Processor Type
|
||||
#
|
||||
CONFIG_CPU_ARM926=y
|
||||
|
||||
|
||||
|
||||
#
|
||||
# ARM Platform Type
|
||||
#
|
||||
|
||||
#
|
||||
# ARM Platform Type
|
||||
#
|
||||
CONFIG_PLATFORM_EB=n
|
||||
CONFIG_PLATFORM_AB926=n
|
||||
CONFIG_PLATFORM_PB926=y
|
||||
|
||||
|
||||
|
||||
#
|
||||
# Platform Drivers
|
||||
#
|
||||
CONFIG_DRIVER_UART_PL011=y
|
||||
CONFIG_DRIVER_TIMER_SP804=y
|
||||
CONFIG_DRIVER_IRQ_PL190=y
|
||||
|
||||
|
||||
CONFIG_CONTAINERS=2
|
||||
|
||||
#
|
||||
# Container Setup
|
||||
#
|
||||
|
||||
#
|
||||
# Container 0 Parameters
|
||||
#
|
||||
|
||||
#
|
||||
# Container 0 Type
|
||||
#
|
||||
CONFIG_CONT0_TYPE_LINUX=n
|
||||
CONFIG_CONT0_TYPE_BARE=n
|
||||
CONFIG_CONT0_TYPE_POSIX=y
|
||||
|
||||
|
||||
#
|
||||
# Container 0 Options
|
||||
#
|
||||
CONFIG_CONT0_OPT_NAME="posix"
|
||||
|
||||
#
|
||||
# Container 0 Default Pager Parameters
|
||||
#
|
||||
CONFIG_CONT0_PAGER_LMA=0x40000
|
||||
CONFIG_CONT0_PAGER_VMA=0xa0000000
|
||||
CONFIG_CONT0_PAGER_SIZE=0xa5000
|
||||
|
||||
|
||||
#
|
||||
# Container 0 POSIX Pager Parameters
|
||||
#
|
||||
CONFIG_CONT0_PAGER_SHM_START=0x40000000
|
||||
CONFIG_CONT0_PAGER_SHM_END=0x50000000
|
||||
CONFIG_CONT0_PAGER_TASK_START=0x30000000
|
||||
CONFIG_CONT0_PAGER_TASK_END=0x40000000
|
||||
CONFIG_CONT0_PAGER_UTCB_START=0xf8100000
|
||||
CONFIG_CONT0_PAGER_UTCB_END=0xf8200000
|
||||
|
||||
|
||||
#
|
||||
# Container 0 Physical Memory Regions
|
||||
#
|
||||
CONFIG_CONT0_PHYSMEM_REGIONS=1
|
||||
|
||||
#
|
||||
# Container 0 Physical Region 0 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT0_PHYS0_START=0x40000
|
||||
CONFIG_CONT0_PHYS0_END=0x1000000
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_READ=y
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
|
||||
#
|
||||
# Container 0 Virtual Memory Regions
|
||||
#
|
||||
CONFIG_CONT0_VIRTMEM_REGIONS=4
|
||||
|
||||
#
|
||||
# Container 0 Virtual Region 0 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT0_VIRT0_START=0xa0000000
|
||||
CONFIG_CONT0_VIRT0_END=0xb0000000
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_UTCB=n
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_READ=y
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
#
|
||||
# Container 0 Virtual Region 1 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT0_VIRT1_START=0x40000000
|
||||
CONFIG_CONT0_VIRT1_END=0x50000000
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_UTCB=n
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_READ=y
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
#
|
||||
# Container 0 Virtual Region 2 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT0_VIRT2_START=0xf8100000
|
||||
CONFIG_CONT0_VIRT2_END=0xf8200000
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_UTCB=y
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_READ=y
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
#
|
||||
# Container 0 Virtual Region 3 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT0_VIRT3_START=0x30000000
|
||||
CONFIG_CONT0_VIRT3_END=0x40000000
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_UTCB=n
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_READ=y
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#
|
||||
# Container 1 Parameters
|
||||
#
|
||||
|
||||
#
|
||||
# Container 1 Type
|
||||
#
|
||||
CONFIG_CONT1_TYPE_LINUX=n
|
||||
CONFIG_CONT1_TYPE_BARE=n
|
||||
CONFIG_CONT1_TYPE_POSIX=y
|
||||
|
||||
|
||||
#
|
||||
# Container 1 Options
|
||||
#
|
||||
CONFIG_CONT1_OPT_NAME="posix1"
|
||||
|
||||
#
|
||||
# Container 1 Default Pager Parameters
|
||||
#
|
||||
CONFIG_CONT1_PAGER_LMA=0x1000000
|
||||
CONFIG_CONT1_PAGER_VMA=0xb0000000
|
||||
CONFIG_CONT1_PAGER_SIZE=0xa5000
|
||||
|
||||
|
||||
#
|
||||
# Container 1 POSIX Pager Parameters
|
||||
#
|
||||
CONFIG_CONT1_PAGER_SHM_START=0x20000000
|
||||
CONFIG_CONT1_PAGER_SHM_END=0x30000000
|
||||
CONFIG_CONT1_PAGER_TASK_START=0x10000000
|
||||
CONFIG_CONT1_PAGER_TASK_END=0x20000000
|
||||
CONFIG_CONT1_PAGER_UTCB_START=0xf8200000
|
||||
CONFIG_CONT1_PAGER_UTCB_END=0xf8300000
|
||||
|
||||
|
||||
#
|
||||
# Container 1 Physical Memory Regions
|
||||
#
|
||||
CONFIG_CONT1_PHYSMEM_REGIONS=1
|
||||
|
||||
#
|
||||
# Container 1 Physical Region 0 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT1_PHYS0_START=0x1000000
|
||||
CONFIG_CONT1_PHYS0_END=0x2000000
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_READ=y
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
|
||||
#
|
||||
# Container 1 Virtual Memory Regions
|
||||
#
|
||||
CONFIG_CONT1_VIRTMEM_REGIONS=4
|
||||
|
||||
#
|
||||
# Container 1 Virtual Region 0 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT1_VIRT0_START=0x10000000
|
||||
CONFIG_CONT1_VIRT0_END=0x20000000
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_UTCB=n
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_READ=y
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
#
|
||||
# Container 1 Virtual Region 1 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT1_VIRT1_START=0x20000000
|
||||
CONFIG_CONT1_VIRT1_END=0x30000000
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_UTCB=n
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_READ=y
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
#
|
||||
# Container 1 Virtual Region 2 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT1_VIRT2_START=0xb0000000
|
||||
CONFIG_CONT1_VIRT2_END=0xc0000000
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_UTCB=n
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_READ=y
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
#
|
||||
# Container 1 Virtual Region 3 Memory Capabilities
|
||||
#
|
||||
CONFIG_CONT1_VIRT3_START=0xf8200000
|
||||
CONFIG_CONT1_VIRT3_END=0xf8300000
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_UTCB=y
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_READ=y
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_WRITE=y
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_EXEC=y
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_UNMAP=y
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#
|
||||
# Derived symbols
|
||||
#
|
||||
CONFIG_CONT1_PHYS1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT1_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT2_VIRT2_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT0_PHYS2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_VIRT4_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_VIRT2_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT0_PHYS1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_VIRT3_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT2_VIRT5_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT0_VIRT4_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT3_VIRT1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_PHYS3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_PHYS0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_UTCB_=1
|
||||
CONFIG_CONT3_VIRT1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_PHYS1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_PHYS0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT3_VIRT2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_PHYS1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_PHYS1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_PHYS3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_VIRT3_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_VIRT5_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT3_VIRT4_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT4_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT3_VIRT3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_PHYS1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_VIRT5_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_PHYS2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT4_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT0_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT1_VIRT5_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_VIRT5_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_VIRT5_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_PHYS0_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_PHYS3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_VIRT5_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_PHYS2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_PHYS2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_VIRT5_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_PHYS1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_VIRT3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_PHYS3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_VIRT5_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_PHYS1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_VIRT3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_PHYS1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_VIRT4_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_PHYS0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_PHYS2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_VIRT4_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_PHYS3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_VIRT0_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT0_PHYS2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_PHYS1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_PHYS3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT5_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_VIRT4_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT2_PHYS0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_VIRT4_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_PHYS2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT4_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_VIRT1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_PHYS3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_PHYS2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT5_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT1_PHYS2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_VIRT2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_PHYS2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_VIRT3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_VIRT5_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT4_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_VIRT3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_PHYS2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_PHYS0_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_PHYS3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_PHYS2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_PHYS3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_VIRT5_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_VIRT5_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_PHYS2_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_VIRT5_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT1_VIRT4_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_VIRT1_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT0_PHYS0_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_VIRT3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_VIRT4_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_VIRT4_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_VIRT2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_PHYS0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_PHYS1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_PHYS3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_PHYS2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_VIRT0_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT0_VIRT4_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_PHYS2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_VIRT0_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_VIRT4_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT5_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_PHYS1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_PHYS1_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_VIRT0_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT2_CAP_MAP_READ_=1
|
||||
CONFIG_CONT2_VIRT1_CAP_MAP_READ_=1
|
||||
CONFIG_CONT1_PHYS3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT0_VIRT5_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_VIRT4_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_PHYS3_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT0_VIRT3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT5_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT1_PHYS1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_VIRT4_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_PHYS3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_PHYS3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT1_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT3_VIRT5_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_PHYS0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_VIRT4_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_VIRT0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT3_VIRT0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_VIRT1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT3_VIRT2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_VIRT3_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT1_PHYS0_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT2_VIRT0_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_VIRT4_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT3_VIRT5_CAP_MAP_UTCB_=0
|
||||
CONFIG_CONT0_VIRT1_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_PHYS2_CAP_MAP_UNMAP_=1
|
||||
CONFIG_CONT0_VIRT2_CAP_MAP_UTCB_=1
|
||||
CONFIG_CONT1_PHYS3_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT2_PHYS3_CAP_MAP_READ_=1
|
||||
CONFIG_CONT3_VIRT2_CAP_MAP_WRITE_=1
|
||||
CONFIG_CONT2_PHYS1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT3_PHYS1_CAP_MAP_EXEC_=1
|
||||
CONFIG_CONT1_VIRT0_CAP_MAP_EXEC_=1
|
||||
#
|
||||
# That's all, folks!
|
||||
Reference in New Issue
Block a user