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Taking UART code out from libc and loader and putting in libdev

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This commit is contained in:
Amit Mahajan
2009-11-05 23:45:11 +05:30
parent 272b01d873
commit c44d25b596
18 changed files with 334 additions and 861 deletions
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8
loader/libs/c/SConscript
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@@ -15,12 +15,12 @@ sys.path.append(PROJRELROOT)
from config.configuration import *
from config.projpaths import *
Import('env', 'arch', 'platform')
variant = 'baremetal'
Import('env', 'arch', 'platform', 'type')
variant = type
e = env.Clone()
e.Append(CPPPATH = ['include/sys-' + variant + '/arch-' + arch])
e.Append(CCFLAGS = ['-nostdinc', ('-D' + platform)])
e.Append(CPPPATH = ['include/sys-' + variant + '/arch-' + arch],
CCFLAGS = ['-nostdinc', '-DVARIANT_' + variant.upper()])
source = \
Glob('src/*.c') + \

380
loader/libs/c/include/arch/pl011_uart.h
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@@ -1,380 +0,0 @@
#ifndef __PL011__UART__H__
#define __PL011__UART__H__
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2006
*
* The particular intention of this code is that it has been carefully
* written as decoupled from os-specific code and in a verbose way such
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* and implementing a driver from scratch. This is the very first to be
* such a driver so far, hopefully it will turn out to be useful.
*/
/* Select the physcial base address of UART0 based on platform selected */
#if defined(pb926)
#define PL011_DEFAULT_PHYSICAL_BASE 0x101F1000
#elif defined(eb)
#define PL011_DEFAULT_PHYSICAL_BASE 0x10009000
#elif defined(pb11mpcore)
#define PL011_DEFAULT_PHYSICAL_BASE 0x10009000
#elif defined(pba8)
#define PL011_DEFAULT_PHYSICAL_BASE 0x10009000
#endif
#define PL011_BASE PL011_DEFAULT_PHYSICAL_BASE
/* Architecture specific memory access macros */
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
/* Register offsets */
#define PL011_UARTDR 0x00
#define PL011_UARTRSR 0x04
#define PL011_UARTECR 0x04
#define PL011_UARTFR 0x18
#define PL011_UARTILPR 0x20
#define PL011_UARTIBRD 0x24
#define PL011_UARTFBRD 0x28
#define PL011_UARTLCR_H 0x2C
#define PL011_UARTCR 0x30
#define PL011_UARTIFLS 0x34
#define PL011_UARTIMSC 0x38
#define PL011_UARTRIS 0x3C
#define PL011_UARTMIS 0x40
#define PL011_UARTICR 0x44
#define PL011_UARTDMACR 0x48
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
#define PL011_TXIRQ (1 << 5)
#define PL011_RXTIMEOUTIRQ (1 << 6)
#define PL011_FEIRQ (1 << 7)
#define PL011_PEIRQ (1 << 8)
#define PL011_BEIRQ (1 << 9)
#define PL011_OEIRQ (1 << 10)
/* FIXME: Need to define this somewhere else */
struct pl011_uart uart;
int pl011_initialise(struct pl011_uart *uart);
int pl011_tx_char(unsigned int base, char c);
int pl011_rx_char(unsigned int base, char *c);
void pl011_set_baudrate(unsigned int base, unsigned int baud,
unsigned int clkrate);
void pl011_set_irq_mask(unsigned int base, unsigned int flags);
void pl011_clr_irq_mask(unsigned int base, unsigned int flags);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *uart, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *uart, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *uart, unsigned int);
static inline void pl011_uart_enable(unsigned int base);
static inline void pl011_uart_disable(unsigned int base);
static inline void pl011_tx_enable(unsigned int base);
static inline void pl011_tx_disable(unsigned int base);
static inline void pl011_rx_enable(unsigned int base);
static inline void pl011_rx_disable(unsigned int base);
static inline void pl011_irq_clear(unsigned int base, unsigned int flags);
static inline unsigned int pl011_read_irqstat(unsigned int base);
static inline unsigned int pl011_read_irqmask(unsigned int base);
static inline void pl011_rx_dma_disable(unsigned int base);
static inline void pl011_rx_dma_enable(unsigned int base);
static inline void pl011_tx_dma_enable(unsigned int base);
static inline void pl011_tx_dma_disable(unsigned int base);
static inline void pl011_set_irq_fifolevel(unsigned int base,
unsigned int xfer, unsigned int level);
static inline void pl011_set_word_width(unsigned int base, int size);
static inline void pl011_disable_fifos(unsigned int base);
static inline void pl011_set_parity_even(unsigned int base);
static inline void pl011_parity_enable(unsigned int base);
static inline void pl011_set_stopbits(unsigned int base, int stopbits);
static inline void pl011_set_parity_odd(unsigned int base);
static inline void pl011_enable_fifos(unsigned int base);
static inline void pl011_parity_disable(unsigned int base);
struct pl011_uart {
unsigned int base;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
unsigned int overrun_errors;
unsigned int rx_timeout_errors;
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val |= PL011_UARTEN;
write(val, (base + PL011_UARTCR));
return;
}
static inline void pl011_uart_disable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val &= ~PL011_UARTEN;
write(val, (base + PL011_UARTCR));
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val |= PL011_TXE;
write(val, (base + PL011_UARTCR));
return;
}
static inline void pl011_tx_disable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val &= ~PL011_TXE;
write(val, (base + PL011_UARTCR));
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val |= PL011_RXE;
write(val, (base + PL011_UARTCR));
return;
}
static inline void pl011_rx_disable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val &= ~PL011_RXE;
write(val, (base + PL011_UARTCR));
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(unsigned int base, int stopbits)
{
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
if(stopbits == 2) { /* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, (base + PL011_UARTLCR_H));
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable(unsigned int base)
{
unsigned int val = 0;
read(val, (base +PL011_UARTLCR_H));
val |= PL011_PARITY_ENABLE;
write(val, (base + PL011_UARTLCR_H));
return;
}
static inline void pl011_parity_disable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_ENABLE;
write(val, (base + PL011_UARTLCR_H));
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val |= PL011_PARITY_EVEN;
write(val, (base + PL011_UARTLCR_H));
return;
}
static inline void pl011_set_parity_odd(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_EVEN;
write(val, (base + PL011_UARTLCR_H));
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val |= PL011_ENABLE_FIFOS;
write(val, (base + PL011_UARTLCR_H));
return;
}
static inline void pl011_disable_fifos(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val &= ~PL011_ENABLE_FIFOS;
write(val, (base + PL011_UARTLCR_H));
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(unsigned int base, int size)
{
unsigned int val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, (base + PL011_UARTLCR_H));
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, (base + PL011_UARTLCR_H));
/*
* The formula is to write 5 less of size given:
* 11 = 8 bits
* 10 = 7 bits
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, (base + PL011_UARTLCR_H));
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, (base + PL011_UARTLCR_H));
return;
}
/*
* Defines at which level of fifo fullness an irq will be generated.
* @xfer: tx fifo = 0, rx fifo = 1
* @level: Generate irq if:
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int base, \
unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), (base + PL011_UARTIFLS));
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(unsigned int base)
{
unsigned int flags;
read(flags, (base + PL011_UARTIMSC));
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(unsigned int base)
{
unsigned int irqstatus;
read(irqstatus, (base + PL011_UARTMIS));
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int base, unsigned int flags)
{
if(flags > 0x3FF) {
/* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, (base + PL011_UARTICR));
return;
}
#define PL011_TXDMAEN (1 << 1)
#define PL011_RXDMAEN (1 << 0)
/*
* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val |= PL011_TXDMAEN;
write(val, (base + PL011_UARTDMACR));
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val &= ~PL011_TXDMAEN;
write(val, (base + PL011_UARTDMACR));
return;
}
static inline void pl011_rx_dma_enable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val |= PL011_RXDMAEN;
write(val, (base + PL011_UARTDMACR));
return;
}
static inline void pl011_rx_dma_disable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val &= ~PL011_RXDMAEN;
write(val, (base +PL011_UARTDMACR));
return;
}
#endif /* __PL011__UART__ */

52
loader/libs/c/src/sys-baremetal/arch-arm/platform_init.c
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@@ -1,52 +0,0 @@
#include <arch/pl011_uart.h>
struct pl011_uart uart;
void platform_init(void);
void platform_init(void)
{
uart.base = PL011_BASE;
pl011_initialise(&uart);
}
/*
* Initialises the uart class data structures, and the device.
* Terminal-like operation is assumed for default settings.
*/
int pl011_initialise(struct pl011_uart * uart)
{
uart->frame_errors = 0;
uart->parity_errors = 0;
uart->break_errors = 0;
uart->overrun_errors = 0;
/* Initialise data register for 8 bit data read/writes */
pl011_set_word_width(uart->base, 8);
/*
* Fifos are disabled because by default it is assumed the port
* will be used as a user terminal, and in that case the typed
* characters will only show up when fifos are flushed, rather than
* when each character is typed. We avoid this by not using fifos.
*/
pl011_disable_fifos(uart->base);
/* Set default baud rate of 38400 */
pl011_set_baudrate(uart->base, 38400, 24000000);
/* Set default settings of 1 stop bit, no parity, no hw flow ctrl */
pl011_set_stopbits(uart->base, 1);
pl011_parity_disable(uart->base);
/* Disable all irqs */
pl011_set_irq_mask(uart->base, 0x3FF);
/* Enable rx, tx, and uart chip */
pl011_tx_enable(uart->base);
pl011_rx_enable(uart->base);
pl011_uart_enable(uart->base);
return 0;
}

199
loader/libs/c/src/sys-baremetal/arch-arm/sys_fputc.c
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@@ -1,207 +1,14 @@
/*
* Australian Public Licence B (OZPLB)
* Ties up platform's uart driver functions with printf
*
* Version 1-0
* Copyright (C) 2009 B Labs Ltd.
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
#include <stdio.h>
#include <stdint.h>
#include <arch/pl011_uart.h>
#include <pl011_uart.h>
extern struct pl011_uart uart;
/* UART-specific internal error codes */
#define PL011_ERROR 1
#define PL011_EAGAIN 2
/* Error status bits in receive status register */
#define PL011_FE (1 << 0)
#define PL011_PE (1 << 1)
#define PL011_BE (1 << 2)
#define PL011_OE (1 << 3)
/* Status bits in flag register */
#define PL011_TXFE (1 << 7)
#define PL011_RXFF (1 << 6)
#define PL011_TXFF (1 << 5)
#define PL011_RXFE (1 << 4)
#define PL011_BUSY (1 << 3)
#define PL011_DCD (1 << 2)
#define PL011_DSR (1 << 1)
#define PL011_CTS (1 << 0)
int pl011_tx_char(unsigned int base, char c)
{
unsigned int val = 0;
read(val, (base + PL011_UARTFR));
if(val & PL011_TXFF) { /* TX FIFO Full */
return -PL011_EAGAIN;
}
write(c, (base + PL011_UARTDR));
return 0;
}
int pl011_rx_char(unsigned int base, char * c)
{
unsigned int data;
unsigned int val = 0;
read(val, (base + PL011_UARTFR));
if(val & PL011_RXFE) { /* RX FIFO Empty */
return -PL011_EAGAIN;
}
read(data, (base + PL011_UARTDR));
*c = (char) data;
if((data >> 8) & 0xF) { /* There were errors */
return -1; /* Signal error in xfer */
}
return 0; /* No error return */
}
/*
* Sets the baud rate in kbps. It is recommended to use
* standard rates such as: 1200, 2400, 3600, 4800, 7200,
* 9600, 14400, 19200, 28800, 38400, 57600 76800, 115200.
*/
void pl011_set_baudrate(unsigned int base, unsigned int baud,
unsigned int clkrate)
{
const unsigned int uartclk = 24000000; /* 24Mhz clock fixed on pb926 */
unsigned int val = 0;
unsigned int ipart = 0, fpart = 0;
/* Use default pb926 rate if no rate is supplied */
if(clkrate == 0) {
clkrate = uartclk;
}
if(baud > 115200 || baud < 1200) {
baud = 38400; /* Default rate. */
}
ipart = 39; /* clkrate / (16 * baud) */
write(ipart, (base + PL011_UARTIBRD));
write(fpart, (base + PL011_UARTFBRD));
/*
* For the IBAUD and FBAUD to update, we need to
* write to UARTLCR_H because the 3 registers are
* actually part of a single register in hardware
* which only updates by a write to UARTLCR_H
*/
read(val, (base + PL011_UARTLCR_H));
write(val, (base + PL011_UARTLCR_H));
return;
}
/* Masks the irqs given in the flags bitvector. */
void pl011_set_irq_mask(unsigned int base, unsigned int flags)
{
unsigned int val = 0;
if(flags > 0x3FF) {
/* Invalid irqmask bitvector */
return;
}
read(val, (base + PL011_UARTIMSC));
val |= flags;
write(val, (base + PL011_UARTIMSC));
return;
}
/* Clears the irqs given in flags from masking */
void pl011_clr_irq_mask(unsigned int base, unsigned int flags)
{
unsigned int val = 0;
if(flags > 0x3FF) {
/* Invalid irqmask bitvector */
return;
}
read(val, (base + PL011_UARTIMSC));
val &= ~flags;
write(val, (base + PL011_UARTIMSC));
return;
}
int __fputc(int c, FILE *stream)
{
int res;