Initial commit

include/l4/drivers/irq/gic.h

@@ -0,0 +1,13 @@
+/*
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+#ifndef __GIC_H__
+#define __GIC_H__
+
+
+
+
+
+#endif /* __GIC_H__ */

include/l4/drivers/irq/intctrl.h

@@ -0,0 +1,241 @@
+/*********************************************************************
+ *                
+ * Copyright (C) 2004,  National ICT Australia (NICTA)
+ *                
+ * File path:     platform/pleb2/intctrl.h
+ * Description:   
+ *                
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id: intctrl.h,v 1.2 2004/12/02 22:40:44 cvansch Exp $
+ *                
+ ********************************************************************/
+#ifndef __PLATFORM__PB926__INTCTRL_H__
+#define __PLATFORM__PB926__INTCTRL_H__
+
+#include <intctrl.h>
+#include INC_GLUE(hwspace.h)
+#include INC_ARCH(thread.h)
+#include INC_ARCH(clz.h)
+#include INC_API(space.h)
+#include INC_PLAT(offsets.h)
+#include INC_PLAT(timer.h)
+#include INC_CPU(cpu.h)
+
+/* Flags to define Primary and Secondary irq controllers */
+#define PB926_PIC		0
+#define PB926_SIC		1
+
+/* Flags to define fast or normal interrupts */
+#define PB926_IRQ		0
+#define PB926_FIQ		1
+
+
+void vic_init(void);
+
+/* IRQS */
+#define IRQS			64
+
+/* FIXME:
+ * IRQ handler array doesn't match with irq descriptor array, which must be taken as
+ * reference because its indices are unique. Make sure this happens.
+ */
+/* Our major OS timer */
+#define PB926_IRQ_OS_TIMER
+
+/* Virtual offsets from some virtual device base */
+
+/* Absolute virtual addresses */
+#define	PB926_VIC_VBASE		(IODEVICE_VADDR + PB926_VIC_VOFFSET)
+#define	PB926_SIC_VBASE		(IODEVICE_VADDR + PB926_SIC_VOFFSET)
+
+/* Interrupt controller register offsets (absolute virtual) */
+#define PIC_IRQSTATUS			(volatile word_t *)(PB926_VIC_VBASE + 0x00)
+#define PIC_FIQSTATUS			(volatile word_t *)(PB926_VIC_VBASE + 0x04)
+#define PIC_RAWINTR			(volatile word_t *)(PB926_VIC_VBASE + 0x08)
+#define PIC_INTSELECT			(volatile word_t *)(PB926_VIC_VBASE + 0x0C)
+#define PIC_INTENABLE			(volatile word_t *)(PB926_VIC_VBASE + 0x10)
+#define PIC_INTENCLEAR			(volatile word_t *)(PB926_VIC_VBASE + 0x14)
+#define PIC_SOFTINT			(volatile word_t *)(PB926_VIC_VBASE + 0x18)
+#define PIC_SOFTINTCLEAR		(volatile word_t *)(PB926_VIC_VBASE + 0x1C)
+#define PIC_PROTECTION			(volatile word_t *)(PB926_VIC_VBASE + 0x20)
+#define PIC_VECTADDR			(volatile word_t *)(PB926_VIC_VBASE + 0x30)
+#define PIC_DEFVECTADDR			(volatile word_t *)(PB926_VIC_VBASE + 0x34)
+#define PIC_VECTADDR0			(volatile word_t *)(PB926_VIC_VBASE + 0x100)
+/* 15 PIC_VECTADDR registers up to	0x13C */
+#define PIC_VECTCNTL0			(volatile word_t *)(PB926_VIC_VBASE + 0x200)
+/* 15 PIC_VECTCNTL registers up to	0x23C */
+
+#define SIC_STATUS			(volatile word_t *)(PB926_SIC_VBASE + 0x0)
+#define SIC_RAWSTAT			(volatile word_t *)(PB926_SIC_VBASE + 0x04)
+#define SIC_ENABLE			(volatile word_t *)(PB926_SIC_VBASE + 0x08)
+#define SIC_ENSET			(volatile word_t *)(PB926_SIC_VBASE + 0x08)
+#define SIC_ENCLR			(volatile word_t *)(PB926_SIC_VBASE + 0x0C)
+#define SIC_SOFTINTSET			(volatile word_t *)(PB926_SIC_VBASE + 0x10)
+#define SIC_SOFTINTCLR			(volatile word_t *)(PB926_SIC_VBASE + 0x14)
+#define SIC_PICENABLE			(volatile word_t *)(PB926_SIC_VBASE + 0x20)
+#define SIC_PICENSET			(volatile word_t *)(PB926_SIC_VBASE + 0x20)
+#define SIC_PICENCLR			(volatile word_t *)(PB926_SIC_VBASE + 0x24)
+
+/*******************************************/
+
+
+	/* BB:  IRQ Explanation for VIC
+	 * On PB926 there are two interrupt controllers. A secondary IC is 
+	 * cascaded on the primary, using pin 31. We ack irqs by simply clearing
+	 * the status register. We actually ack_and_mask, so for acking, we also 
+	 * disable the particular irq, on either pic or sic.
+	 * 
+	 * What's more to cascaded irq controllers is that, you may have the 
+	 * same line number on different controllers, for different irqs. This
+	 * causes a difficulty to uniquely identify an interrupt, because the 
+	 * line number is not a primary key anymore. One approach is to `assume'
+	 * irqs on one controller are added to the maximum you can have on the 
+	 * other. E.g. irq 1 on intctrl P is 1, but irq 1 on intctrl S is 
+	 * (1 + 31) = 32. While this works, it's not the best approach because 
+	 * you will see that more complicated architectures on SMP machines are 
+	 * present. (See PB1176 or EB port, or even worse, try an ARM11MPCore 
+	 * on EB.)
+	 * 
+	 * What's better is to use a struct to describe what the irq line 
+	 * `actually' is, so things are put straight, with a small memory 
+	 * trade-off.
+	 * 
+	 * Furthermore to this, each irq is described uniquely by an irq
+	 * descriptor; however, we still need the simplicity of a single integer
+	 * to uniquely identify each individual irq. This integer, is the index
+	 * of each irq descriptor, in the array of irq descriptors. This index
+	 * is not necessarily a natural mapping from irq numbers in interrupt
+	 * controllers, as described in paragraph 2, but it is rather a compile-
+	 * time constant as far as the compile-time defined irq array is
+	 * concerned, or, the set of such primary keys may expand as the array
+	 * expands dynamically at run-time (e.g. registration of new irqs at
+	 * run-time).
+	 */
+
+extern word_t arm_high_vector; 
+extern word_t interrupt_handlers[IRQS];
+class intctrl_t : public generic_intctrl_t {
+	
+/* Timer needs to know about its irq, stored in this class. */
+friend class arm_sp804timer;
+
+/* Defines an irq on pb926 */
+public:
+struct pb926dev_irq {
+	int intctrl;	/* The irq controller this irq is on */
+	int irqno;	/* The pin (i.e. line) on this controller */
+	int irqtype;	/* Fast, or normal. IRQ = 0, FIQ = 1 */
+};
+
+/* TODO: The reason our static variables aren't static anymore is that,
+ * they need to be instantiated and initialised in global scope, in order to be
+ * used. E.g:
+ * intctrl_t::pb926_irq_watchdog = { 1, 3, 4 }; 
+ * I haven't figured out where and how to initialise them this way yet, thus
+ * they're non-static for now. 
+ */
+
+#if 0
+/* IRQ definitions */
+static struct pb926dev_irq pb926_irq_watchdog = {
+	//.intctrl= PB926_PIC,
+	//.irqno	= 0,
+	//.irqtype= PB926_IRQ
+PB926_PIC, 0, PB926_IRQ
+};
+static struct pb926dev_irq pb926_irq_timer0_1 = {
+//	.intctrl= PB926_PIC,
+//	.irqno	= 4,
+//	.irqtype= PB926_IRQ
+PB926_PIC, 4, PB926_IRQ
+};
+#endif
+
+struct pb926dev_irq pb926_irq_watchdog;
+struct pb926dev_irq pb926_irq_timer0_1;
+struct pb926dev_irq pb926_irq_uart0;
+struct pb926dev_irq * irq_desc_array[IRQS];
+
+public:
+
+void init_cpu();
+
+void init_arch(void)
+{
+	pb926_irq_watchdog.intctrl = PB926_PIC;
+	pb926_irq_watchdog.irqno   = 0;
+	pb926_irq_watchdog.irqtype = PB926_IRQ;
+	
+	pb926_irq_timer0_1.intctrl = PB926_PIC;
+	pb926_irq_timer0_1.irqno   = 4;
+	pb926_irq_timer0_1.irqtype = PB926_IRQ;
+	
+	pb926_irq_uart0.intctrl = PB926_PIC;
+	pb926_irq_uart0.irqno   = 12;
+	pb926_irq_uart0.irqtype = PB926_IRQ;
+
+	irq_desc_array[0] = &pb926_irq_watchdog;
+	irq_desc_array[4] = &pb926_irq_timer0_1;
+	irq_desc_array[12]= &pb926_irq_uart0;
+
+	vic_init();
+}
+
+int irq_number(void);
+void ack(int irqno);
+void mask(int irqno);
+int unmask(int irq);
+bool is_irq_available(int irq);
+
+word_t get_number_irqs(void)
+{
+	return IRQS;
+}
+
+void register_interrupt_handler (word_t vector, void (*handler)(word_t,
+	arm_irq_context_t *))
+{
+	ASSERT(DEBUG, vector < IRQS);
+	interrupt_handlers[vector] = (word_t) handler;
+	TRACE_INIT("interrupt vector[%d] = %p\n", vector, 
+	interrupt_handlers[vector]);
+}
+
+
+inline void disable(int irq)
+{  
+	mask(irq);
+}
+
+inline int enable(int irq)
+{
+	return unmask(irq);
+}
+
+void disable_fiq(void) {}
+
+
+void set_cpu(word_t irq, word_t cpu) {}
+
+}; 
+#endif /*__PLATFORM__PB926__INTCTRL_H__ */

include/l4/drivers/irq/pl190/intctrl.h

@@ -0,0 +1,241 @@
+/*********************************************************************
+ *                
+ * Copyright (C) 2004,  National ICT Australia (NICTA)
+ *                
+ * File path:     platform/pleb2/intctrl.h
+ * Description:   
+ *                
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id: intctrl.h,v 1.2 2004/12/02 22:40:44 cvansch Exp $
+ *                
+ ********************************************************************/
+#ifndef __PLATFORM__PB926__INTCTRL_H__
+#define __PLATFORM__PB926__INTCTRL_H__
+
+#include <intctrl.h>
+#include INC_GLUE(hwspace.h)
+#include INC_ARCH(thread.h)
+#include INC_ARCH(clz.h)
+#include INC_API(space.h)
+#include INC_PLAT(offsets.h)
+#include INC_PLAT(timer.h)
+#include INC_CPU(cpu.h)
+
+/* Flags to define Primary and Secondary irq controllers */
+#define PB926_PIC		0
+#define PB926_SIC		1
+
+/* Flags to define fast or normal interrupts */
+#define PB926_IRQ		0
+#define PB926_FIQ		1
+
+
+void vic_init(void);
+
+/* IRQS */
+#define IRQS			64
+
+/* FIXME:
+ * IRQ handler array doesn't match with irq descriptor array, which must be taken as
+ * reference because its indices are unique. Make sure this happens.
+ */
+/* Our major OS timer */
+#define PB926_IRQ_OS_TIMER
+
+/* Virtual offsets from some virtual device base */
+
+/* Absolute virtual addresses */
+#define	PB926_VIC_VBASE		(IODEVICE_VADDR + PB926_VIC_VOFFSET)
+#define	PB926_SIC_VBASE		(IODEVICE_VADDR + PB926_SIC_VOFFSET)
+
+/* Interrupt controller register offsets (absolute virtual) */
+#define PIC_IRQSTATUS			(volatile word_t *)(PB926_VIC_VBASE + 0x00)
+#define PIC_FIQSTATUS			(volatile word_t *)(PB926_VIC_VBASE + 0x04)
+#define PIC_RAWINTR			(volatile word_t *)(PB926_VIC_VBASE + 0x08)
+#define PIC_INTSELECT			(volatile word_t *)(PB926_VIC_VBASE + 0x0C)
+#define PIC_INTENABLE			(volatile word_t *)(PB926_VIC_VBASE + 0x10)
+#define PIC_INTENCLEAR			(volatile word_t *)(PB926_VIC_VBASE + 0x14)
+#define PIC_SOFTINT			(volatile word_t *)(PB926_VIC_VBASE + 0x18)
+#define PIC_SOFTINTCLEAR		(volatile word_t *)(PB926_VIC_VBASE + 0x1C)
+#define PIC_PROTECTION			(volatile word_t *)(PB926_VIC_VBASE + 0x20)
+#define PIC_VECTADDR			(volatile word_t *)(PB926_VIC_VBASE + 0x30)
+#define PIC_DEFVECTADDR			(volatile word_t *)(PB926_VIC_VBASE + 0x34)
+#define PIC_VECTADDR0			(volatile word_t *)(PB926_VIC_VBASE + 0x100)
+/* 15 PIC_VECTADDR registers up to	0x13C */
+#define PIC_VECTCNTL0			(volatile word_t *)(PB926_VIC_VBASE + 0x200)
+/* 15 PIC_VECTCNTL registers up to	0x23C */
+
+#define SIC_STATUS			(volatile word_t *)(PB926_SIC_VBASE + 0x0)
+#define SIC_RAWSTAT			(volatile word_t *)(PB926_SIC_VBASE + 0x04)
+#define SIC_ENABLE			(volatile word_t *)(PB926_SIC_VBASE + 0x08)
+#define SIC_ENSET			(volatile word_t *)(PB926_SIC_VBASE + 0x08)
+#define SIC_ENCLR			(volatile word_t *)(PB926_SIC_VBASE + 0x0C)
+#define SIC_SOFTINTSET			(volatile word_t *)(PB926_SIC_VBASE + 0x10)
+#define SIC_SOFTINTCLR			(volatile word_t *)(PB926_SIC_VBASE + 0x14)
+#define SIC_PICENABLE			(volatile word_t *)(PB926_SIC_VBASE + 0x20)
+#define SIC_PICENSET			(volatile word_t *)(PB926_SIC_VBASE + 0x20)
+#define SIC_PICENCLR			(volatile word_t *)(PB926_SIC_VBASE + 0x24)
+
+/*******************************************/
+
+
+	/* BB:  IRQ Explanation for VIC
+	 * On PB926 there are two interrupt controllers. A secondary IC is 
+	 * cascaded on the primary, using pin 31. We ack irqs by simply clearing
+	 * the status register. We actually ack_and_mask, so for acking, we also 
+	 * disable the particular irq, on either pic or sic.
+	 * 
+	 * What's more to cascaded irq controllers is that, you may have the 
+	 * same line number on different controllers, for different irqs. This
+	 * causes a difficulty to uniquely identify an interrupt, because the 
+	 * line number is not a primary key anymore. One approach is to `assume'
+	 * irqs on one controller are added to the maximum you can have on the 
+	 * other. E.g. irq 1 on intctrl P is 1, but irq 1 on intctrl S is 
+	 * (1 + 31) = 32. While this works, it's not the best approach because 
+	 * you will see that more complicated architectures on SMP machines are 
+	 * present. (See PB1176 or EB port, or even worse, try an ARM11MPCore 
+	 * on EB.)
+	 * 
+	 * What's better is to use a struct to describe what the irq line 
+	 * `actually' is, so things are put straight, with a small memory 
+	 * trade-off.
+	 * 
+	 * Furthermore to this, each irq is described uniquely by an irq
+	 * descriptor; however, we still need the simplicity of a single integer
+	 * to uniquely identify each individual irq. This integer, is the index
+	 * of each irq descriptor, in the array of irq descriptors. This index
+	 * is not necessarily a natural mapping from irq numbers in interrupt
+	 * controllers, as described in paragraph 2, but it is rather a compile-
+	 * time constant as far as the compile-time defined irq array is
+	 * concerned, or, the set of such primary keys may expand as the array
+	 * expands dynamically at run-time (e.g. registration of new irqs at
+	 * run-time).
+	 */
+
+extern word_t arm_high_vector; 
+extern word_t interrupt_handlers[IRQS];
+class intctrl_t : public generic_intctrl_t {
+	
+/* Timer needs to know about its irq, stored in this class. */
+friend class arm_sp804timer;
+
+/* Defines an irq on pb926 */
+public:
+struct pb926dev_irq {
+	int intctrl;	/* The irq controller this irq is on */
+	int irqno;	/* The pin (i.e. line) on this controller */
+	int irqtype;	/* Fast, or normal. IRQ = 0, FIQ = 1 */
+};
+
+/* TODO: The reason our static variables aren't static anymore is that,
+ * they need to be instantiated and initialised in global scope, in order to be
+ * used. E.g:
+ * intctrl_t::pb926_irq_watchdog = { 1, 3, 4 }; 
+ * I haven't figured out where and how to initialise them this way yet, thus
+ * they're non-static for now. 
+ */
+
+#if 0
+/* IRQ definitions */
+static struct pb926dev_irq pb926_irq_watchdog = {
+	//.intctrl= PB926_PIC,
+	//.irqno	= 0,
+	//.irqtype= PB926_IRQ
+PB926_PIC, 0, PB926_IRQ
+};
+static struct pb926dev_irq pb926_irq_timer0_1 = {
+//	.intctrl= PB926_PIC,
+//	.irqno	= 4,
+//	.irqtype= PB926_IRQ
+PB926_PIC, 4, PB926_IRQ
+};
+#endif
+
+struct pb926dev_irq pb926_irq_watchdog;
+struct pb926dev_irq pb926_irq_timer0_1;
+struct pb926dev_irq pb926_irq_uart0;
+struct pb926dev_irq * irq_desc_array[IRQS];
+
+public:
+
+void init_cpu();
+
+void init_arch(void)
+{
+	pb926_irq_watchdog.intctrl = PB926_PIC;
+	pb926_irq_watchdog.irqno   = 0;
+	pb926_irq_watchdog.irqtype = PB926_IRQ;
+	
+	pb926_irq_timer0_1.intctrl = PB926_PIC;
+	pb926_irq_timer0_1.irqno   = 4;
+	pb926_irq_timer0_1.irqtype = PB926_IRQ;
+	
+	pb926_irq_uart0.intctrl = PB926_PIC;
+	pb926_irq_uart0.irqno   = 12;
+	pb926_irq_uart0.irqtype = PB926_IRQ;
+
+	irq_desc_array[0] = &pb926_irq_watchdog;
+	irq_desc_array[4] = &pb926_irq_timer0_1;
+	irq_desc_array[12]= &pb926_irq_uart0;
+
+	vic_init();
+}
+
+int irq_number(void);
+void ack(int irqno);
+void mask(int irqno);
+int unmask(int irq);
+bool is_irq_available(int irq);
+
+word_t get_number_irqs(void)
+{
+	return IRQS;
+}
+
+void register_interrupt_handler (word_t vector, void (*handler)(word_t,
+	arm_irq_context_t *))
+{
+	ASSERT(DEBUG, vector < IRQS);
+	interrupt_handlers[vector] = (word_t) handler;
+	TRACE_INIT("interrupt vector[%d] = %p\n", vector, 
+	interrupt_handlers[vector]);
+}
+
+
+inline void disable(int irq)
+{  
+	mask(irq);
+}
+
+inline int enable(int irq)
+{
+	return unmask(irq);
+}
+
+void disable_fiq(void) {}
+
+
+void set_cpu(word_t irq, word_t cpu) {}
+
+}; 
+#endif /*__PLATFORM__PB926__INTCTRL_H__ */

include/l4/drivers/irq/pl190/pl190_vic.h

@@ -0,0 +1,56 @@
+/*
+ * PL190 Primecell Vectored Interrupt Controller offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PL190_VIC_H__
+#define __PL190_VIC_H__
+
+#include INC_PLAT(platform.h)
+
+#define PL190_BASE				PLATFORM_IRQCTRL_BASE
+#define PL190_SIC_BASE				PLATFORM_SIRQCTRL_BASE
+
+/* VIC register offsets */
+#define PL190_VIC_IRQSTATUS			(PL190_BASE + 0x00)
+#define PL190_VIC_FIQSTATUS			(PL190_BASE + 0x04)
+#define PL190_VIC_RAWINTR			(PL190_BASE + 0x08)
+#define PL190_VIC_INTSELECT			(PL190_BASE + 0x0C)
+#define PL190_VIC_INTENABLE			(PL190_BASE + 0x10)
+#define PL190_VIC_INTENCLEAR			(PL190_BASE + 0x14)
+#define PL190_VIC_SOFTINT			(PL190_BASE + 0x18)
+#define PL190_VIC_SOFTINTCLEAR			(PL190_BASE + 0x1C)
+#define PL190_VIC_PROTECTION			(PL190_BASE + 0x20)
+#define PL190_VIC_VECTADDR			(PL190_BASE + 0x30)
+#define PL190_VIC_DEFVECTADDR			(PL190_BASE + 0x34)
+#define PL190_VIC_VECTADDR0			(PL190_BASE + 0x100)
+/* 15 PIC_VECTADDR registers up to	0x13C */
+#define PL190_VIC_VECTCNTL0			(PL190_BASE + 0x200)
+/* 15 PIC_VECTCNTL registers up to	0x23C */
+
+#define PL190_SIC_STATUS			(PL190_SIC_BASE + 0x0)
+#define PL190_SIC_RAWSTAT			(PL190_SIC_BASE + 0x04)
+#define PL190_SIC_ENABLE			(PL190_SIC_BASE + 0x08)
+#define PL190_SIC_ENSET				(PL190_SIC_BASE + 0x08)
+#define PL190_SIC_ENCLR				(PL190_SIC_BASE + 0x0C)
+#define PL190_SIC_SOFTINTSET			(PL190_SIC_BASE + 0x10)
+#define PL190_SIC_SOFTINTCLR			(PL190_SIC_BASE + 0x14)
+#define PL190_SIC_PICENABLE			(PL190_SIC_BASE + 0x20)
+#define PL190_SIC_PICENSET			(PL190_SIC_BASE + 0x20)
+#define PL190_SIC_PICENCLR			(PL190_SIC_BASE + 0x24)
+
+void pl190_vic_init(void);
+void pl190_ack_irq(int irq);
+void pl190_mask_irq(int irq);
+void pl190_unmask_irq(int irq);
+int pl190_read_irq(void);
+
+int pl190_sic_read_irq(void);
+void pl190_sic_mask_irq(int irq);
+void pl190_sic_mask_irq(int irq);
+void pl190_sic_ack_irq(int irq);
+void pl190_sic_unmask_irq(int irq);
+void pl190_sic_init(void);
+#endif /* __PL190_VIC_H__ */

include/l4/drivers/misc/sp810/sp810_sysctrl.h

@@ -0,0 +1,54 @@
+/*
+ * SP810 Primecell system controller offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __SP810_SYSCTRL_H__
+#define __SP810_SYSCTRL_H__
+
+#include INC_PLAT(platform.h)
+
+/* FIXME: Fix the stupid uart driver and change to single definition of this! */
+#if defined(read)
+#undef read
+#endif
+#if defined(write)
+#undef write
+#endif
+
+#define		read(a)		*((volatile unsigned int *)(a))
+#define		write(v, a)	(*((volatile unsigned int *)(a)) = v)
+#define		setbit(bit, a)	write(read(a) | bit, a)
+#define		clrbit(bit, a)  write(read(a) & ~bit, a)
+#define		devio(base, reg, bit, setclr)			\
+			(setclr) ? setbit(bit, base + reg)	\
+			: clrbit(bit, base + reg)
+
+/* The SP810 system controller offsets */
+#define SP810_BASE			PLATFORM_SP810_BASE
+#define SP810_SCCTRL			(SP810_BASE + 0x0)
+/* ... Fill in as needed. */
+
+
+/* Set clock source for timers on this platform.
+ * @timer: The index of timer you want to set the clock for.
+ * On PB926 valid values are 0-4.
+ *
+ * @freq: The frequency you want to set the timer for.
+ * On PB926 valid values are 32KHz = 0 (0 is 32Khz because that's
+ * the default.) and 1MHz = non-zero.
+ */
+static inline void sp810_set_timclk(int timer, unsigned int freq)
+{
+	if (timer < 0 || timer > 3)
+		return;
+
+	freq ? setbit((1 << (15 + (2 * timer))), SP810_SCCTRL) :
+	clrbit((1 << (15 + (2 * timer))), SP810_SCCTRL);
+
+	return;
+}
+
+#endif /* __SP810_SYSCTRL_H__ */

include/l4/drivers/timer/sp804/sp804_timer.h

@@ -0,0 +1,27 @@
+/*
+ * SP804 Primecell Timer offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+#ifndef __SP804_TIMER_H__
+#define __SP804_TIMER_H__
+
+#include INC_PLAT(platform.h)
+
+#define SP804_TIMER01_BASE		PLATFORM_TIMER_BASE
+
+#define SP804_TIMER1LOAD		(SP804_TIMER01_BASE + 0x0)
+#define SP804_TIMER1VALUE		(SP804_TIMER01_BASE + 0x4)
+#define SP804_TIMER1CONTROL		(SP804_TIMER01_BASE + 0x8)
+#define SP804_TIMER1INTCLR		(SP804_TIMER01_BASE + 0xC)
+#define SP804_TIMER1RIS			(SP804_TIMER01_BASE + 0x10)
+#define SP804_TIMER1MIS			(SP804_TIMER01_BASE + 0x14)
+#define SP804_TIMER1BGLOAD		(SP804_TIMER01_BASE + 0x18)
+#define SP804_TIMER2OFFSET		0x20
+
+void sp804_init(void);
+void sp804_irq_handler(void);
+void sp804_enable(int timer, int enable);
+void sp804_set_irq(int timer, int enable);
+#endif /* __SP804_TIMER_H__ */

include/l4/drivers/uart/pl011/pl011_uart.h

@@ -0,0 +1,380 @@
+/*
+ * PL011 UART Generic driver implementation.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ * The particular intention of this code is that it has been carefully written
+ * as decoupled from os-specific code and in a verbose way such that it clearly
+ * demonstrates how the device operates, reducing the amount of time to be spent
+ * for understanding the operational model and implementing a driver from
+ * scratch. This is the very first to be such a driver so far, hopefully it will
+ * turn out to be useful.
+ */
+
+#ifndef __PL011_UART_H__
+#define __PL011_UART_H__
+
+#include INC_PLAT(uart.h)
+#include INC_ARCH(io.h)
+
+#define PL011_BASE		PLATFORM_CONSOLE_BASE
+
+/* Register offsets */
+#define PL011_UARTDR		(PL011_BASE + 0x00)
+#define PL011_UARTRSR		(PL011_BASE + 0x04)
+#define PL011_UARTECR		(PL011_BASE + 0x04)
+#define PL011_UARTFR		(PL011_BASE + 0x18)
+#define PL011_UARTILPR		(PL011_BASE + 0x20)
+#define PL011_UARTIBRD		(PL011_BASE + 0x24)
+#define PL011_UARTFBRD		(PL011_BASE + 0x28)
+#define PL011_UARTLCR_H		(PL011_BASE + 0x2C)
+#define PL011_UARTCR		(PL011_BASE + 0x30)
+#define PL011_UARTIFLS		(PL011_BASE + 0x34)
+#define PL011_UARTIMSC		(PL011_BASE + 0x38)
+#define PL011_UARTRIS		(PL011_BASE + 0x3C)
+#define PL011_UARTMIS		(PL011_BASE + 0x40)
+#define PL011_UARTICR		(PL011_BASE + 0x44)
+#define PL011_UARTDMACR		(PL011_BASE + 0x48)
+
+/* IRQ bits for each uart irq event */
+#define PL011_RXIRQ		(1 << 4)
+#define PL011_TXIRQ		(1 << 5)
+#define PL011_RXTIMEOUTIRQ	(1 << 6)
+#define PL011_FEIRQ		(1 << 7)
+#define PL011_PEIRQ		(1 << 8)
+#define PL011_BEIRQ		(1 << 9)
+#define PL011_OEIRQ		(1 << 10)
+
+struct pl011_uart;
+
+void pl011_initialise_driver();
+
+int pl011_initialise_device(struct pl011_uart *);
+
+int pl011_tx_char(char);
+int pl011_rx_char(char *);
+
+void pl011_set_baudrate(unsigned int, unsigned int);
+void pl011_set_irq_mask(unsigned int);
+void pl011_clr_irq_mask(unsigned int);
+
+void pl011_irq_handler(struct pl011_uart *);
+void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
+void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
+void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
+
+struct pl011_uart_ops {
+	int  (*initialise)(struct pl011_uart *);
+
+	int  (*tx_char)(char);
+	int  (*rx_char)(char *);
+
+	void (*set_baudrate)(unsigned int, unsigned int);
+	void (*set_irq_mask)(unsigned int);
+	void (*clr_irq_mask)(unsigned int);
+
+	void (*irq_handler)(struct pl011_uart *);
+	void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
+	void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
+	void (*error_irq_handler)(struct pl011_uart *, unsigned int);
+};
+
+struct pl011_uart {
+	unsigned int base;
+	struct pl011_uart_ops ops;
+	unsigned int frame_errors;
+	unsigned int parity_errors;
+	unsigned int break_errors;
+	unsigned int overrun_errors;
+	unsigned int rx_timeout_errors;
+};
+
+#define PL011_UARTEN	(1 << 0)
+static inline void pl011_uart_enable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTCR);
+	val |= PL011_UARTEN;
+	write(val, PL011_UARTCR);
+
+	return;
+}
+
+static inline void pl011_uart_disable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTCR);
+	val &= ~PL011_UARTEN;
+	write(val, PL011_UARTCR);
+
+	return;
+}
+
+#define PL011_TXE	(1 << 8)
+static inline void pl011_tx_enable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTCR);
+	val |= PL011_TXE;
+	write(val, PL011_UARTCR);
+	return;
+}
+
+static inline void pl011_tx_disable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTCR);
+	val &= ~PL011_TXE;
+	write(val, PL011_UARTCR);
+	return;
+}
+
+
+#define PL011_RXE	(1 << 9)
+static inline void pl011_rx_enable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTCR);
+	val |= PL011_RXE;
+	write(val, PL011_UARTCR);
+	return;
+}
+
+static inline void pl011_rx_disable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTCR);
+	val &= ~PL011_RXE;
+	write(val, PL011_UARTCR);
+	return;
+}
+
+#define PL011_TWO_STOPBITS_SELECT	(1 << 3)
+static inline void pl011_set_stopbits(int stopbits)
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTLCR_H);
+
+	if(stopbits == 2) {			/* Set to two bits */
+		val |= PL011_TWO_STOPBITS_SELECT;
+	} else {				/* Default is 1 */
+		val &= ~PL011_TWO_STOPBITS_SELECT;
+	}
+	write(val, PL011_UARTLCR_H);
+	return;
+}
+
+#define PL011_PARITY_ENABLE	(1 << 1)
+static inline void pl011_parity_enable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTLCR_H);
+	val |= PL011_PARITY_ENABLE;
+	write(val, PL011_UARTLCR_H);
+	return;
+}
+
+static inline void pl011_parity_disable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTLCR_H);
+	val &= ~PL011_PARITY_ENABLE;
+	write(val, PL011_UARTLCR_H);
+	return;
+}
+
+#define PL011_PARITY_EVEN	(1 << 2)
+static inline void pl011_set_parity_even()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTLCR_H);
+	val |= PL011_PARITY_EVEN;
+	write(val, PL011_UARTLCR_H);
+	return;
+}
+
+static inline void pl011_set_parity_odd()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTLCR_H);
+	val &= ~PL011_PARITY_EVEN;
+	write(val, PL011_UARTLCR_H);
+	return;
+}
+
+#define	PL011_ENABLE_FIFOS	(1 << 4)
+static inline void pl011_enable_fifos()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTLCR_H);
+	val |= PL011_ENABLE_FIFOS;
+	write(val, PL011_UARTLCR_H);
+	return;
+}
+
+static inline void pl011_disable_fifos()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTLCR_H);
+	val &= ~PL011_ENABLE_FIFOS;
+	write(val, PL011_UARTLCR_H);
+	return;
+}
+
+#define PL011_WORD_WIDTH_SHIFT	(5)
+/* Sets the transfer word width for the data register. */
+static inline void pl011_set_word_width(int size)
+{
+	unsigned int val;
+	val = 0;
+
+	if(size < 5 || size > 8)	/* Default is 8 */
+		size = 8;
+
+	/* Clear size field */
+	read(val, PL011_UARTLCR_H);
+	val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
+	write(val, PL011_UARTLCR_H);
+
+	/* The formula is to write 5 less of size given:
+	 * 11 = 8 bits
+	 * 10 = 7 bits
+	 * 01 = 6 bits
+	 * 00 = 5 bits
+	 */
+	read(val, PL011_UARTLCR_H);
+	val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
+	write(val, PL011_UARTLCR_H);
+
+	return;
+}
+
+/*
+ * Defines at which level of fifo fullness an irq will be generated.
+ * @xfer: tx fifo = 0, rx fifo = 1
+ * @level: Generate irq if:
+ * 0	rxfifo >= 1/8 full  	txfifo <= 1/8 full
+ * 1	rxfifo >= 1/4 full  	txfifo <= 1/4 full
+ * 2	rxfifo >= 1/2 full  	txfifo <= 1/2 full
+ * 3	rxfifo >= 3/4 full	txfifo <= 3/4 full
+ * 4	rxfifo >= 7/8 full	txfifo <= 7/8 full
+ * 5-7	reserved		reserved
+ */
+static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
+{
+	if(xfer != 1 && xfer != 0)	/* Invalid fifo */
+		return;
+
+	if(level > 4)			/* Invalid level */
+		return;
+
+	write(level << (xfer * 3), PL011_UARTIFLS);
+	return;
+}
+
+/* returns which irqs are masked */
+static inline unsigned int pl011_read_irqmask(void)
+{
+	unsigned int flags;
+	read(flags, PL011_UARTIMSC);
+	return flags;
+}
+
+/* returns masked irq status */
+static inline unsigned int pl011_read_irqstat(void)
+{
+	unsigned int irqstatus;
+	read(irqstatus, PL011_UARTMIS);
+	return irqstatus;
+}
+/* Clears the given asserted irqs */
+static inline void pl011_irq_clear(unsigned int flags)
+{
+	if(flags > 0x3FF) {	/* Invalid irq clearing bitvector */
+		return;
+	}
+	/* Simply write the flags since it's a write-only register */
+	write(flags, PL011_UARTICR);
+	return;
+}
+
+#define PL011_TXDMAEN	(1 << 1)
+#define PL011_RXDMAEN	(1 << 0)
+
+/* Enables dma transfers for uart. The dma controller
+ * must be initialised, set-up and enabled separately.
+ */
+static inline void pl011_tx_dma_enable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTDMACR);
+	val |= PL011_TXDMAEN;
+	write(val, PL011_UARTDMACR);
+	return;
+}
+
+/* Disables dma transfers for uart */
+static inline void pl011_tx_dma_disable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTDMACR);
+	val &= ~PL011_TXDMAEN;
+	write(val, PL011_UARTDMACR);
+	return;
+}
+
+static inline void pl011_rx_dma_enable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTDMACR);
+	val |= PL011_RXDMAEN;
+	write(val, PL011_UARTDMACR);
+	return;
+}
+
+static inline void pl011_rx_dma_disable()
+{
+	unsigned int val;
+	val = 0;
+
+	read(val, PL011_UARTDMACR);
+	val &= ~PL011_RXDMAEN;
+	write(val, PL011_UARTDMACR);
+	return;
+}
+
+
+#endif /* __PL011_UART__ */
+