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Corrected the problem of wrong values in printascii.S

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This commit is contained in:
Amit Mahajan
2009-10-30 12:32:08 +05:30
parent 9463d1f241
commit f337257e4e
5 changed files with 73 additions and 34 deletions
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26
src/platform/eb/printascii.S
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@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word EB_UART0_BASE
/*
* FIXME: We need to divide into bytes as writing to register doesnot look
* possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE EB_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word EB_UART0_VBASE
#define UART0_VIRT_BASE EB_UART0_VBASE
#define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
#define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
moveq \rx, #UART0_PHYS_BYTE1
orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm
.macro uart_send, ry, rx

26
src/platform/pb11mpcore/printascii.S
View File

@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word PB11MPCORE_UART0_BASE
/*
* FIXME: We need to divide into bytes as writing to register doesnot look
* possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE PB11MPCORE_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word PB11MPCORE_UART0_VBASE
#define UART0_VIRT_BASE PB11MPCORE_UART0_VBASE
#define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
#define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
moveq \rx, #UART0_PHYS_BYTE1
orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm
.macro uart_send, ry, rx

26
src/platform/pb926/printascii.S
View File

@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word PB926_UART0_BASE
/*
* FIXME: We need to divide into bytes as writing to register doesnot look
* possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE PB926_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word PB926_UART0_VBASE
#define UART0_VIRT_BASE PB926_UART0_VBASE
#define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
#define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
moveq \rx, #UART0_PHYS_BYTE1
orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm
.macro uart_send, ry, rx

26
src/platform/pba8/printascii.S
View File

@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word PBA8_UART0_BASE
/*
* FIXME: We need to divide into bytes as writing to register doesnot look
* possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE PBA8_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word PBA8_UART0_VBASE
#define UART0_VIRT_BASE PBA8_UART0_VBASE
#define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
#define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
moveq \rx, #UART0_PHYS_BYTE1
orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm
.macro uart_send, ry, rx