sambuc/codezero
1
0
Fork 0
mirror of https://github.com/drasko/codezero.git synced 2026-02-27 09:13:13 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

Corrected the problem of wrong values in printascii.S

Browse Source
This commit is contained in:
Amit Mahajan
2009-10-30 12:32:08 +05:30
parent 9463d1f241
commit f337257e4e
5 changed files with 73 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
scripts/linux/build_linux.py
View File

@@ -37,8 +37,7 @@ class LinuxUpdateKernel:
['SCSI', 'SET'],['BLK_DEV_SD', 'SET'], ['SCSI', 'SET'],['BLK_DEV_SD', 'SET'],
['SYM53C8XX_2', 'SET'],['INPUT_EVDEV', 'SET'], ['SYM53C8XX_2', 'SET'],['INPUT_EVDEV', 'SET'],
['INOTIFY', 'SET'],['DEBUG_INFO', 'SET'], ['INOTIFY', 'SET'],['DEBUG_INFO', 'SET'],
['USB_SUPPORT', 'UNSET'],['SOUND', 'UNSET'], ['USB_SUPPORT', 'UNSET'],['SOUND', 'UNSET'],)
['MMC', 'UNSET'],)
# List of CPUIDs, to be used by linux based on codezero config # List of CPUIDs, to be used by linux based on codezero config
self.cpuid_list = (['ARM926', '0x41069265'],) self.cpuid_list = (['ARM926', '0x41069265'],)

26
src/platform/eb/printascii.S
View File

@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0 #define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */ /*
uart0_phys_base_addr: * FIXME: We need to divide into bytes as writing to register doesnot look
.word EB_UART0_BASE * possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE EB_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */ #define UART0_VIRT_BASE EB_UART0_VBASE
uart0_virtual_base_addr: #define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
.word EB_UART0_VBASE #define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx .macro uart_address rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled? tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr moveq \rx, #UART0_PHYS_BYTE1
movne \rx, #uart0_virtual_base_addr orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm .endm
.macro uart_send, ry, rx .macro uart_send, ry, rx

26
src/platform/pb11mpcore/printascii.S
View File

@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0 #define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */ /*
uart0_phys_base_addr: * FIXME: We need to divide into bytes as writing to register doesnot look
.word PB11MPCORE_UART0_BASE * possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE PB11MPCORE_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */ #define UART0_VIRT_BASE PB11MPCORE_UART0_VBASE
uart0_virtual_base_addr: #define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
.word PB11MPCORE_UART0_VBASE #define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx .macro uart_address rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled? tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr moveq \rx, #UART0_PHYS_BYTE1
movne \rx, #uart0_virtual_base_addr orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm .endm
.macro uart_send, ry, rx .macro uart_send, ry, rx

26
src/platform/pb926/printascii.S
View File

@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0 #define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */ /*
uart0_phys_base_addr: * FIXME: We need to divide into bytes as writing to register doesnot look
.word PB926_UART0_BASE * possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE PB926_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */ #define UART0_VIRT_BASE PB926_UART0_VBASE
uart0_virtual_base_addr: #define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
.word PB926_UART0_VBASE #define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx .macro uart_address rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled? tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr moveq \rx, #UART0_PHYS_BYTE1
movne \rx, #uart0_virtual_base_addr orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm .endm
.macro uart_send, ry, rx .macro uart_send, ry, rx

26
src/platform/pba8/printascii.S
View File

@@ -8,19 +8,29 @@
#define UART_DATA_OFFSET 0x0 #define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */ /*
uart0_phys_base_addr: * FIXME: We need to divide into bytes as writing to register doesnot look
.word PBA8_UART0_BASE * possible directly, it gives some errors in compilation
*/
#define UART0_PHYS_BASE PBA8_UART0_BASE
#define UART0_PHYS_BYTE1 (UART0_PHYS_BASE & 0xFF000000)
#define UART0_PHYS_BYTE2 (UART0_PHYS_BASE & 0x00FF0000)
#define UART0_PHYS_BYTE3_4 (UART0_PHYS_BASE & 0x0000FFFF)
/* Virtual base address of UART0 */ #define UART0_VIRT_BASE PBA8_UART0_VBASE
uart0_virtual_base_addr: #define UART0_VIRT_BYTE1 (UART0_VIRT_BASE & 0xFF000000)
.word PBA8_UART0_VBASE #define UART0_VIRT_BYTE2 (UART0_VIRT_BASE & 0x00FF0000)
#define UART0_VIRT_BYTE3_4 (UART0_VIRT_BASE & 0x0000FFFF)
.macro uart_address rx .macro uart_address rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled? tst \rx, #1 @ MMU enabled?
moveq \rx, #uart0_phys_base_addr moveq \rx, #UART0_PHYS_BYTE1
movne \rx, #uart0_virtual_base_addr orreq \rx, #UART0_PHYS_BYTE2
orreq \rx, #UART0_PHYS_BYTE3_4
movne \rx, #UART0_VIRT_BYTE1
orrne \rx, #UART0_VIRT_BYTE2
orrne \rx, #UART0_VIRT_BYTE3_4
.endm .endm
.macro uart_send, ry, rx .macro uart_send, ry, rx