mirror of
https://github.com/drasko/codezero.git
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380 lines
9.7 KiB
C
380 lines
9.7 KiB
C
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#ifndef __PL011__UART__H__
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#define __PL011__UART__H__
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/*
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* PL011 UART Generic driver implementation.
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* Copyright Bahadir Balban (C) 2009
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*
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* The particular intention of this code is that it has been carefully
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* written as decoupled from os-specific code and in a verbose way such
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* that it clearly demonstrates how the device operates, reducing the
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* amount of time to be spent for understanding the operational model
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* and implementing a driver from scratch. This is the very first to be
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* such a driver so far, hopefully it will turn out to be useful.
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*/
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#if defined(VARIANT_USERSPACE)
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/* FIXME: Take this value in agreement from kernel, or from kernel only */
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#define PL011_BASE 0x500000
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#endif
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#if defined(VARIANT_BAREMETAL)
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#if defined(PLATFORM_PB926)
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#define PL011_BASE 0x101F1000
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#elif defined(PLATFORM_EB)
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#define PL011_BASE 0x10009000
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#elif defined(PLATFORM_PB11MPCORE)
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#define PL011_BASE 0x10009000
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#endif
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#endif
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/* Architecture specific memory access macros */
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#define read(val, address) val = *((volatile unsigned int *) address)
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#define write(val, address) *((volatile unsigned int *) address) = val
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/* Register offsets */
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#define PL011_UARTDR 0x00
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#define PL011_UARTRSR 0x04
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#define PL011_UARTECR 0x04
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#define PL011_UARTFR 0x18
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#define PL011_UARTILPR 0x20
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#define PL011_UARTIBRD 0x24
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#define PL011_UARTFBRD 0x28
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#define PL011_UARTLCR_H 0x2C
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#define PL011_UARTCR 0x30
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#define PL011_UARTIFLS 0x34
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#define PL011_UARTIMSC 0x38
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#define PL011_UARTRIS 0x3C
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#define PL011_UARTMIS 0x40
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#define PL011_UARTICR 0x44
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#define PL011_UARTDMACR 0x48
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/* IRQ bits for each uart irq event */
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#define PL011_RXIRQ (1 << 4)
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#define PL011_TXIRQ (1 << 5)
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#define PL011_RXTIMEOUTIRQ (1 << 6)
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#define PL011_FEIRQ (1 << 7)
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#define PL011_PEIRQ (1 << 8)
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#define PL011_BEIRQ (1 << 9)
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#define PL011_OEIRQ (1 << 10)
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struct pl011_uart {
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unsigned long base;
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unsigned int frame_errors;
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unsigned int parity_errors;
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unsigned int break_errors;
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unsigned int overrun_errors;
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unsigned int rx_timeout_errors;
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};
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int pl011_tx_char(unsigned int base, char c);
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int pl011_rx_char(unsigned int base, char *c);
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void pl011_set_baudrate(unsigned int base, unsigned int baud,
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unsigned int clkrate);
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void pl011_set_irq_mask(unsigned int base, unsigned int flags);
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void pl011_clr_irq_mask(unsigned int base, unsigned int flags);
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void pl011_irq_handler(struct pl011_uart *);
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void pl011_tx_irq_handler(struct pl011_uart *uart, unsigned int);
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void pl011_rx_irq_handler(struct pl011_uart *uart, unsigned int);
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void pl011_error_irq_handler(struct pl011_uart *uart, unsigned int);
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static inline void pl011_uart_enable(unsigned int base);
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static inline void pl011_uart_disable(unsigned int base);
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static inline void pl011_tx_enable(unsigned int base);
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static inline void pl011_tx_disable(unsigned int base);
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static inline void pl011_rx_enable(unsigned int base);
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static inline void pl011_rx_disable(unsigned int base);
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static inline void pl011_irq_clear(unsigned int base, unsigned int flags);
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static inline unsigned int pl011_read_irqstat(unsigned int base);
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static inline unsigned int pl011_read_irqmask(unsigned int base);
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static inline void pl011_rx_dma_disable(unsigned int base);
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static inline void pl011_rx_dma_enable(unsigned int base);
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static inline void pl011_tx_dma_enable(unsigned int base);
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static inline void pl011_tx_dma_disable(unsigned int base);
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static inline void pl011_set_irq_fifolevel(unsigned int base,
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unsigned int xfer, unsigned int level);
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static inline void pl011_set_word_width(unsigned int base, int size);
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static inline void pl011_disable_fifos(unsigned int base);
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static inline void pl011_set_parity_even(unsigned int base);
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static inline void pl011_parity_enable(unsigned int base);
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static inline void pl011_set_stopbits(unsigned int base, int stopbits);
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static inline void pl011_set_parity_odd(unsigned int base);
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static inline void pl011_enable_fifos(unsigned int base);
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static inline void pl011_parity_disable(unsigned int base);
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#define PL011_UARTEN (1 << 0)
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static inline void pl011_uart_enable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTCR));
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val |= PL011_UARTEN;
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write(val, (base + PL011_UARTCR));
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return;
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}
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static inline void pl011_uart_disable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTCR));
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val &= ~PL011_UARTEN;
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write(val, (base + PL011_UARTCR));
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return;
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}
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#define PL011_TXE (1 << 8)
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static inline void pl011_tx_enable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTCR));
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val |= PL011_TXE;
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write(val, (base + PL011_UARTCR));
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return;
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}
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static inline void pl011_tx_disable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTCR));
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val &= ~PL011_TXE;
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write(val, (base + PL011_UARTCR));
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return;
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}
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#define PL011_RXE (1 << 9)
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static inline void pl011_rx_enable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTCR));
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val |= PL011_RXE;
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write(val, (base + PL011_UARTCR));
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return;
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}
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static inline void pl011_rx_disable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTCR));
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val &= ~PL011_RXE;
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write(val, (base + PL011_UARTCR));
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return;
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}
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#define PL011_TWO_STOPBITS_SELECT (1 << 3)
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static inline void pl011_set_stopbits(unsigned int base, int stopbits)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTLCR_H));
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if(stopbits == 2) { /* Set to two bits */
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val |= PL011_TWO_STOPBITS_SELECT;
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} else { /* Default is 1 */
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val &= ~PL011_TWO_STOPBITS_SELECT;
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}
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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#define PL011_PARITY_ENABLE (1 << 1)
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static inline void pl011_parity_enable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base +PL011_UARTLCR_H));
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val |= PL011_PARITY_ENABLE;
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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static inline void pl011_parity_disable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTLCR_H));
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val &= ~PL011_PARITY_ENABLE;
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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#define PL011_PARITY_EVEN (1 << 2)
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static inline void pl011_set_parity_even(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTLCR_H));
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val |= PL011_PARITY_EVEN;
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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static inline void pl011_set_parity_odd(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTLCR_H));
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val &= ~PL011_PARITY_EVEN;
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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#define PL011_ENABLE_FIFOS (1 << 4)
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static inline void pl011_enable_fifos(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTLCR_H));
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val |= PL011_ENABLE_FIFOS;
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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static inline void pl011_disable_fifos(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTLCR_H));
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val &= ~PL011_ENABLE_FIFOS;
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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#define PL011_WORD_WIDTH_SHIFT (5)
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/* Sets the transfer word width for the data register. */
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static inline void pl011_set_word_width(unsigned int base, int size)
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{
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unsigned int val = 0;
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if(size < 5 || size > 8) /* Default is 8 */
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size = 8;
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/* Clear size field */
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read(val, (base + PL011_UARTLCR_H));
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val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
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write(val, (base + PL011_UARTLCR_H));
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/*
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* The formula is to write 5 less of size given:
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* 11 = 8 bits
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* 10 = 7 bits
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* 01 = 6 bits
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* 00 = 5 bits
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*/
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read(val, (base + PL011_UARTLCR_H));
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val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
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write(val, (base + PL011_UARTLCR_H));
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return;
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}
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/*
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* Defines at which level of fifo fullness an irq will be generated.
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* @xfer: tx fifo = 0, rx fifo = 1
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* @level: Generate irq if:
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* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
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* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
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* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
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* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
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* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
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* 5-7 reserved reserved
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*/
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static inline void pl011_set_irq_fifolevel(unsigned int base, \
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unsigned int xfer, unsigned int level)
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{
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if(xfer != 1 && xfer != 0) /* Invalid fifo */
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return;
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if(level > 4) /* Invalid level */
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return;
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write(level << (xfer * 3), (base + PL011_UARTIFLS));
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return;
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}
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/* returns which irqs are masked */
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static inline unsigned int pl011_read_irqmask(unsigned int base)
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{
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unsigned int flags;
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read(flags, (base + PL011_UARTIMSC));
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return flags;
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}
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/* returns masked irq status */
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static inline unsigned int pl011_read_irqstat(unsigned int base)
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{
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unsigned int irqstatus;
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read(irqstatus, (base + PL011_UARTMIS));
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return irqstatus;
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}
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/* Clears the given asserted irqs */
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static inline void pl011_irq_clear(unsigned int base, unsigned int flags)
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{
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if(flags > 0x3FF) {
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/* Invalid irq clearing bitvector */
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return;
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}
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/* Simply write the flags since it's a write-only register */
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write(flags, (base + PL011_UARTICR));
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return;
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}
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#define PL011_TXDMAEN (1 << 1)
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#define PL011_RXDMAEN (1 << 0)
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/*
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* Enables dma transfers for uart. The dma controller
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* must be initialised, set-up and enabled separately.
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*/
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static inline void pl011_tx_dma_enable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTDMACR));
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val |= PL011_TXDMAEN;
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write(val, (base + PL011_UARTDMACR));
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return;
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}
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/* Disables dma transfers for uart */
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static inline void pl011_tx_dma_disable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTDMACR));
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val &= ~PL011_TXDMAEN;
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write(val, (base + PL011_UARTDMACR));
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return;
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}
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static inline void pl011_rx_dma_enable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTDMACR));
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val |= PL011_RXDMAEN;
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write(val, (base + PL011_UARTDMACR));
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return;
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}
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static inline void pl011_rx_dma_disable(unsigned int base)
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{
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unsigned int val = 0;
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read(val, (base + PL011_UARTDMACR));
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val &= ~PL011_RXDMAEN;
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write(val, (base +PL011_UARTDMACR));
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return;
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}
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int pl011_initialise(struct pl011_uart *uart);
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#endif /* __PL011__UART__ */
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