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72 lines
2.6 KiB
C
72 lines
2.6 KiB
C
/*
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* Describes physical memory layout of EB platform.
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#ifndef __PLATFORM_EB_OFFSETS_H__
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#define __PLATFORM_EB_OFFSETS_H__
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/* Physical memory base */
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#define PHYS_MEM_START 0x00000000 /* inclusive */
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#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
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/*
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* These bases taken from where kernel is `physically' linked at,
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* also used to calculate virtual-to-physical translation offset.
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* See the linker script for their sources. PHYS_ADDR_BASE can't
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* use a linker variable because it's referred from assembler.
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*/
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#define PHYS_ADDR_BASE 0x100000
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/* Device memory base */
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#define EB_DEV_PHYS 0x10000000
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/* Device offsets in physical memory */
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#define EB_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define EB_SYSCTRL_BASE 0x10001000 /* System controller */
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#define EB_UART0_BASE 0x10009000 /* UART 0 */
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#define EB_UART1_BASE 0x1000A000 /* UART 1 */
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#define EB_UART2_BASE 0x1000B000 /* UART 2 */
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#define EB_UART3_BASE 0x1000C000 /* UART 3 */
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#define EB_WATCHDOG0_BASE 0x10010000 /* WATCHDOG */
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#define EB_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
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#define EB_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
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#define EB_RTC_BASE 0x10017000 /* RTC interface */
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#define EB_GIC0_BASE 0x10040000 /* GIC 0 */
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#define EB_GIC1_BASE 0x10050000 /* GIC 1 */
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#define EB_GIC2_BASE 0x10060000 /* GIC 2 */
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#define EB_GIC3_BASE 0x10070000 /* GIC 3 */
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/*
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* Uart virtual address until a file-based console access
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* is available for userspace
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*/
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#define USERSPACE_UART_BASE 0x500000
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/*
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* Device offsets in virtual memory. They offset to some virtual
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* device base address. Each page on this virtual base is consecutively
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* allocated to devices. Nice and smooth.
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*/
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#define EB_SYSREGS_VOFFSET 0x00000000
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#define EB_SYSCTRL_VOFFSET 0x00001000
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#define EB_UART0_VOFFSET 0x00002000
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#define EB_TIMER01_VOFFSET 0x00003000
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#define EB_GIC0_VOFFSET 0x00004000
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#define EB_GIC1_VOFFSET 0x00005000
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#define EB_GIC2_VOFFSET 0x00006000
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#define EB_GIC3_VOFFSET 0x00007000
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#define EB_SYSREGS_VBASE (IO_AREA0_VADDR + EB_SYSREGS_VOFFSET)
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#define EB_SYSCTRL_VBASE (IO_AREA0_VADDR + EB_SYSCTRL_VOFFSET)
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#define EB_UART0_VBASE (IO_AREA0_VADDR + EB_UART0_VOFFSET)
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#define EB_TIMER01_VBASE (IO_AREA0_VADDR + EB_TIMER01_VOFFSET)
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#define EB_GIC0_VBASE (IO_AREA0_VADDR + EB_GIC0_VOFFSET)
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#define EB_GIC1_VBASE (IO_AREA0_VADDR + EB_GIC1_VOFFSET)
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#define EB_GIC2_VBASE (IO_AREA0_VADDR + EB_GIC2_VOFFSET)
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#define EB_GIC3_VBASE (IO_AREA0_VADDR + EB_GIC3_VOFFSET)
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#endif /* __PLATFORM_EB_OFFSETS_H__ */
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