force a single codegen unit on the dev profile

to work around problems with several codegen units, which is now the default for unoptimized builds

.cargo/config

@@ -1,4 +1,5 @@
 [target.thumbv6m-none-eabi]
+runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
   "-C", "linker=arm-none-eabi-ld",
@@ -6,6 +7,7 @@ rustflags = [
 ]
 
 [target.thumbv7m-none-eabi]
+runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
   "-C", "linker=arm-none-eabi-ld",
@@ -13,6 +15,7 @@ rustflags = [
 ]
 
 [target.thumbv7em-none-eabi]
+runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
   "-C", "linker=arm-none-eabi-ld",
@@ -20,6 +23,7 @@ rustflags = [
 ]
 
 [target.thumbv7em-none-eabihf]
+runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
   "-C", "linker=arm-none-eabi-ld",

.gdbinit

@@ -1,9 +1,18 @@
 target remote :3333
+
 monitor arm semihosting enable
-# if using ITM
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
 # monitor tpiu config internal itm.fifo uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
 # monitor itm port 0 on
+
 load
-tbreak cortex_m_rt::reset_handler
-monitor reset halt
-continue
+step

CHANGELOG.md

@@ -5,7 +5,40 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-## v0.1.4 - 2017-05-13
+## [v0.1.8] - 2017-05-30
+
+### Changed
+
+- Bumped the cortex-m-rt dependency to v0.2.3, and documented the `_stext`
+  symbol (see memory.x).
+
+## [v0.1.7] - 2017-05-27
+
+### Added
+
+- Documentation and an example about how to use the heap and a dynamic memory
+  allocator.
+
+### Changed
+
+- Bumped the `cortex-m-rt` dependency to v0.2.2
+- Bumped the `cortex-m` dependency to v0.2.7
+
+## [v0.1.6] - 2017-05-26
+
+### Added
+
+- Set the default runner in .cargo/config to `arm-none-eabi-gdb`. Now `xargo
+  run` will build the program and start a debug session.
+
+## [v0.1.5] - 2017-05-16
+
+### Added
+
+- A warning about using CARGO_INCREMENTAL to the how to use and the
+  troubleshooting sections.
+
+## [v0.1.4] - 2017-05-13
 
 ### Added
 
@@ -15,7 +48,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 - Extend troubleshooting section
 
-## v0.1.3 - 2017-05-13
+## [v0.1.3] - 2017-05-13
 
 ### Added
 
@@ -25,13 +58,13 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 - Bumped the cortex-m crate version to v0.2.6
 
-## v0.1.2 - 2017-05-07
+## [v0.1.2] - 2017-05-07
 
 ### Fixed
 
 - .gdbinit: jump to reset handler after loading the program.
 
-## v0.1.1 - 2017-04-27
+## [v0.1.1] - 2017-04-27
 
 ### Changed
 
@@ -43,7 +76,11 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 - Initial release
 
-[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.4...HEAD
+[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.8...HEAD
+[v0.1.8]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.7...v0.1.8
+[v0.1.7]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.6...v0.1.7
+[v0.1.6]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.5...v0.1.6
+[v0.1.5]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.4...v0.1.5
 [v0.1.4]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.3...v0.1.4
 [v0.1.3]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.2...v0.1.3
 [v0.1.2]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.1...v0.1.2

Cargo.toml

@@ -6,11 +6,14 @@ keywords = ["arm", "cortex-m", "template"]
 license = "MIT OR Apache-2.0"
 name = "cortex-m-quickstart"
 repository = "https://github.com/japaric/cortex-m-quickstart"
-version = "0.1.4"
+version = "0.1.9"
 
 [dependencies]
-cortex-m = "0.2.6"
-cortex-m-rt = "0.2.0"
+cortex-m = "0.2.7"
+cortex-m-rt = "0.2.3"
+
+[profile.dev]
+codegen-units = 1
 
 [profile.release]
 lto = true

examples/allocator.rs

@@ -0,0 +1,71 @@
+//! How to use the heap and a dynamic memory allocator
+//!
+//! To compile this example you'll need to build the collections crate as part
+//! of the Xargo sysroot. To do that change the Xargo.toml file to look like
+//! this:
+//!
+//! ``` text
+//! [dependencies.core]
+//! [dependencies.collections] # new
+//!
+//! [dependencies.compiler_builtins]
+//! features = ["mem"]
+//! git = "https://github.com/rust-lang-nursery/compiler-builtins"
+//! stage = 1
+//! ```
+//!
+//! This example depends on the alloc-cortex-m crate so you'll have to add it
+//! to your Cargo.toml:
+//!
+//! ``` text
+//! # or edit the Cargo.toml file manually
+//! $ cargo add alloc-cortex-m
+//! ```
+
+#![feature(collections)]
+#![feature(used)]
+#![no_std]
+
+// This is the allocator crate; you can use a different one
+extern crate alloc_cortex_m;
+#[macro_use]
+extern crate collections;
+#[macro_use]
+extern crate cortex_m;
+extern crate cortex_m_rt;
+
+use cortex_m::asm;
+
+fn main() {
+    // Initialize the allocator
+    unsafe {
+        extern "C" {
+            // Start of the heap
+            static mut _sheap: usize;
+        }
+
+        // Size of the heap in words (1 word = 4 bytes)
+        // WARNING: The bigger the heap the greater the chance to run into a
+        // stack overflow (collision between the stack and the heap)
+        const SIZE: isize = 256;
+
+        // End of the heap
+        let _eheap = (&mut _sheap as *mut _).offset(SIZE);
+
+        alloc_cortex_m::init(&mut _sheap as *mut _, _eheap);
+    }
+
+    // Growable array allocated on the heap
+    let xs = vec![0, 1, 2];
+    hprintln!("{:?}", xs);
+}
+
+// As we are not using interrupts, we just register a dummy catch all handler
+#[allow(dead_code)]
+#[used]
+#[link_section = ".rodata.interrupts"]
+static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
+
+extern "C" fn default_handler() {
+    asm::bkpt();
+}

gen-examples.sh

@@ -11,6 +11,7 @@ main() {
         crash
         register-interrupt-handler
         override-exception-handler
+        allocator
     )
 
     rm -rf src/examples

memory.x

@@ -10,3 +10,10 @@ MEMORY
 /* The stack is of the full descending type. */
 /* NOTE Do NOT modify `_stack_start` unless you know what you are doing */
 _stack_start = ORIGIN(RAM) + LENGTH(RAM);
+
+/* You can use this symbol to customize the location of the .text section */
+/* If omitted the .text section will be placed right after the .vector_table
+   section */
+/* This is required only on some microcontrollers that store some configuration
+   right after the vector table */
+/* _stext = ORIGIN(FLASH) + 0x400; */

src/examples/_3_crash.rs

@@ -27,7 +27,7 @@
 //! $2 = cortex_m::exception::Exception::HardFault
 //!
 //! (gdb) # Where did we come from?
-//! (gdb) print _e
+//! (gdb) backtrace
 //! ```
 //!
 //! ```

src/examples/_6_allocator.rs

@@ -0,0 +1,75 @@
+//! How to use the heap and a dynamic memory allocator
+//!
+//! To compile this example you'll need to build the collections crate as part
+//! of the Xargo sysroot. To do that change the Xargo.toml file to look like
+//! this:
+//!
+//! ``` text
+//! [dependencies.core]
+//! [dependencies.collections] # new
+//!
+//! [dependencies.compiler_builtins]
+//! features = ["mem"]
+//! git = "https://github.com/rust-lang-nursery/compiler-builtins"
+//! stage = 1
+//! ```
+//!
+//! This example depends on the alloc-cortex-m crate so you'll have to add it
+//! to your Cargo.toml:
+//!
+//! ``` text
+//! # or edit the Cargo.toml file manually
+//! $ cargo add alloc-cortex-m
+//! ```
+//!
+//! ```
+//! 
+//! #![feature(collections)]
+//! #![feature(used)]
+//! #![no_std]
+//! 
+//! // This is the allocator crate; you can use a different one
+//! extern crate alloc_cortex_m;
+//! #[macro_use]
+//! extern crate collections;
+//! #[macro_use]
+//! extern crate cortex_m;
+//! extern crate cortex_m_rt;
+//! 
+//! use cortex_m::asm;
+//! 
+//! fn main() {
+//!     // Initialize the allocator
+//!     unsafe {
+//!         extern "C" {
+//!             // Start of the heap
+//!             static mut _sheap: usize;
+//!         }
+//! 
+//!         // Size of the heap in words (1 word = 4 bytes)
+//!         // WARNING: The bigger the heap the greater the chance to run into a
+//!         // stack overflow (collision between the stack and the heap)
+//!         const SIZE: isize = 256;
+//! 
+//!         // End of the heap
+//!         let _eheap = (&mut _sheap as *mut _).offset(SIZE);
+//! 
+//!         alloc_cortex_m::init(&mut _sheap as *mut _, _eheap);
+//!     }
+//! 
+//!     // Growable array allocated on the heap
+//!     let xs = vec![0, 1, 2];
+//!     hprintln!("{:?}", xs);
+//! }
+//! 
+//! // As we are not using interrupts, we just register a dummy catch all handler
+//! #[allow(dead_code)]
+//! #[used]
+//! #[link_section = ".rodata.interrupts"]
+//! static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
+//! 
+//! extern "C" fn default_handler() {
+//!     asm::bkpt();
+//! }
+//! ```
+// Auto-generated. Do not modify.

src/examples/mod.rs

@@ -6,3 +6,4 @@ pub mod _2_panic;
 pub mod _3_crash;
 pub mod _4_register_interrupt_handler;
 pub mod _5_override_exception_handler;
+pub mod _6_allocator;

src/lib.rs

@@ -74,6 +74,13 @@
 //! $ rm -r src/* && cp examples/hello.rs src/main.rs
 //! ```
 //!
+//! - Disable incremental compilation. It doesn't work for embedded development.
+//!   You'll hit nonsensical linker errors if you use it.
+//!
+//! ``` text
+//! $ unset CARGO_INCREMENTAL
+//! ```
+//!
 //! - Build the application
 //!
 //! ``` text
@@ -104,16 +111,26 @@
 //!
 //! - Flash the program
 //!
-//! ```
+//! ``` text
 //! # Launch OpenOCD on a terminal
 //! $ openocd -f (..)
 //! ```
 //!
-//! ```
+//! ``` text
 //! # Start debug session
 //! $ arm-none-eabi-gdb target/..
 //! ```
 //!
+//! **NOTE** As of nightly-2017-05-14 or so and cortex-m-quickstart v0.1.6 you
+//! can simply run `cargo run` or `cargo run --example $example` to build the
+//! program, and immediately start a debug session. IOW, it lets you omit the
+//! `arm-none-eabi-gdb` command.
+//!
+//! ``` text
+//! $ cargo run --example hello
+//! > # drops you into a GDB session
+//! ```
+//!
 //! # Examples
 //!
 //! Check the [examples module](./examples/index.html)
@@ -221,6 +238,30 @@
 //!
 //! Solution: Switch to the nightly toolchain with `rustup default nightly`.
 //!
+//! ## Used `CARGO_INCREMENTAL=1`
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ xargo build
+//! error: linking with `arm-none-eabi-ld` failed: exit code: 1
+//!     |
+//! = note: "arm-none-eabi-ld" (..)
+//!     = note: arm-none-eabi-ld:
+//! You must specify the exception handlers.
+//!     Create a non `pub` static variable with type
+//!     `cortex_m::exception::Handlers` and place it in the
+//!     '.rodata.exceptions' section. (cf. #[link_section]). Apply the
+//!     `#[used]` attribute to the variable to make it reach the linker.
+//!     arm-none-eabi-ld:
+//! Invalid '.rodata.exceptions' section.
+//!     Make sure to place a static with type `cortex_m::exception::Handlers`
+//!     in that section (cf. #[link_section]) ONLY ONCE.
+//! ```
+//!
+//! Solution: `$ unset CARGO_INCREMENAL`. And to be on the safe side, call
+//! `cargo clean` and thrash the Xargo sysroot: `$ rm -rf ~/.xargo`
+//!
 //! ## Used `gdb` instead of `arm-none-eabi-gdb`
 //!
 //! Error message: