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adding two examples that are somewhat position independent, wherever the GPU places this code

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it will work (so long as it is not too close to zero, and a 4 byte aligned address of course).
This commit is contained in:
David Welch
2012-07-06 02:36:01 -04:00
parent 1521436e4f
commit 11e7b38f4b
17 changed files with 1055 additions and 0 deletions
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53
zero_start/Makefile Normal file
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ARMGNU ?= arm-none-eabi
COPS = -Wall -O2 -nostdlib -nostartfiles -ffreestanding
all : uart02.bin blinker05.bin
clean :
rm -f *.o
rm -f *.bin
rm -f *.hex
rm -f *.elf
rm -f *.list
rm -f *.img
rm -f *.bc
rm -f *.clang.opt.s
vectors.o : vectors.s
$(ARMGNU)-as vectors.s -o vectors.o
uart02.o : uart02.c
$(ARMGNU)-gcc $(COPS) -c uart02.c -o uart02.o
uart02.elf : memmap vectors.o uart02.o
$(ARMGNU)-ld vectors.o uart02.o -T memmap -o uart02.elf
$(ARMGNU)-objdump -D uart02.elf > uart02.list
uart02.bin : uart02.elf
$(ARMGNU)-objcopy uart02.elf -O binary uart02.bin
uart02.hex : uart02.elf
$(ARMGNU)-objcopy uart02.elf -O ihex uart02.hex
bvectors.o : bvectors.s
$(ARMGNU)-as bvectors.s -o bvectors.o
blinker05.o : blinker05.c
$(ARMGNU)-gcc $(COPS) -c blinker05.c -o blinker05.o
blinker05.elf : memmap bvectors.o blinker05.o
$(ARMGNU)-ld bvectors.o blinker05.o -T memmap -o blinker05.elf
$(ARMGNU)-objdump -D blinker05.elf > blinker05.list
blinker05.bin : blinker05.elf
$(ARMGNU)-objcopy blinker05.elf -O binary blinker05.bin
blinker05.hex : blinker05.elf
$(ARMGNU)-objcopy blinker05.elf -O ihex blinker05.hex

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See the top level README for information on where to find the
schematic and programmers reference manual for the ARM processor
on the raspberry pi. Also find information on how to load and run
these programs.
There are two programs here one is blinker05 and the other uart02.
The difference from their originals is the boot code. In attempt
to not care about where the gpu loads our program (so long as it is
not really close to zero), the startup code looks to see if we booted
at zero, if not, it copies the program from where it is to zero, then
branches to zero. Some linker script items were required to make this
work. First ram starts at 0x0000, that is where we are going to
copy our file. Second, the size of .text is added as a variable.
We can use this variable to connect to the startup code (vectors.s).
The bootcode for blinker05 had another modification, since the linker
is going to think that 0x0000 is the entry point it is going to make
the reset_handler variable contain some number like 0x0040, so right after
you start running that program it branches to zero which has who knows
what code, and you are stuck. That first instruction needs to be a
branch not an ldr pc of some linker filled in value.

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//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
extern void PUT32 ( unsigned int, unsigned int );
extern unsigned int GET32 ( unsigned int );
extern void dummy ( unsigned int );
extern void enable_irq ( void );
extern void enable_fiq ( void );
#define ARM_TIMER_LOD 0x2000B400
#define ARM_TIMER_VAL 0x2000B404
#define ARM_TIMER_CTL 0x2000B408
#define ARM_TIMER_CLI 0x2000B40C
#define ARM_TIMER_RIS 0x2000B410
#define ARM_TIMER_MIS 0x2000B414
#define ARM_TIMER_RLD 0x2000B418
#define ARM_TIMER_DIV 0x2000B41C
#define ARM_TIMER_CNT 0x2000B420
#define SYSTIMERCLO 0x20003004
#define GPFSEL1 0x20200004
#define GPSET0 0x2020001C
#define GPCLR0 0x20200028
#define IRQ_BASIC 0x2000B200
#define IRQ_PEND1 0x2000B204
#define IRQ_PEND2 0x2000B208
#define IRQ_FIQ_CONTROL 0x2000B210
#define IRQ_ENABLE_BASIC 0x2000B218
#define IRQ_DISABLE_BASIC 0x2000B224
volatile unsigned int icount;
//-------------------------------------------------------------------------
void c_irq_handler ( void )
{
icount++;
if(icount&1)
{
PUT32(GPCLR0,1<<16);
}
else
{
PUT32(GPSET0,1<<16);
}
PUT32(ARM_TIMER_CLI,0);
}
//-------------------------------------------------------------------------
int notmain ( void )
{
unsigned int ra;
PUT32(IRQ_DISABLE_BASIC,1);
ra=GET32(GPFSEL1);
ra&=~(7<<18);
ra|=1<<18;
PUT32(GPFSEL1,ra);
PUT32(GPSET0,1<<16);
PUT32(ARM_TIMER_CTL,0x003E0000);
PUT32(ARM_TIMER_LOD,1000000-1);
PUT32(ARM_TIMER_RLD,1000000-1);
PUT32(ARM_TIMER_DIV,0x000000F9);
PUT32(ARM_TIMER_CLI,0);
PUT32(ARM_TIMER_CTL,0x003E00A2);
for(ra=0;ra<5;ra++)
{
PUT32(GPCLR0,1<<16);
while(1) if(GET32(ARM_TIMER_MIS)) break;
PUT32(ARM_TIMER_CLI,0);
PUT32(GPSET0,1<<16);
while(1) if(GET32(ARM_TIMER_MIS)) break;
PUT32(ARM_TIMER_CLI,0);
}
PUT32(ARM_TIMER_LOD,2000000-1);
PUT32(ARM_TIMER_RLD,2000000-1);
PUT32(ARM_TIMER_CLI,0);
PUT32(IRQ_ENABLE_BASIC,1);
for(ra=0;ra<5;ra++)
{
PUT32(GPCLR0,1<<16);
while(1) if(GET32(IRQ_BASIC)&1) break;
PUT32(ARM_TIMER_CLI,0);
PUT32(GPSET0,1<<16);
while(1) if(GET32(IRQ_BASIC)&1) break;
PUT32(ARM_TIMER_CLI,0);
}
PUT32(ARM_TIMER_LOD,4000000-1);
PUT32(ARM_TIMER_RLD,4000000-1);
icount=0;
enable_irq();
while(1) continue;
return(0);
}
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//
// Copyright (c) 2012 David Welch dwelch@dwelch.com
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//-------------------------------------------------------------------------

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blinker05.elf: file format elf32-littlearm
Disassembly of section .text:
00000000 <_start>:
0: ea00000f b 44 <reset>
4: e59ff014 ldr pc, [pc, #20] ; 20 <undefined_handler>
8: e59ff014 ldr pc, [pc, #20] ; 24 <swi_handler>
c: e59ff014 ldr pc, [pc, #20] ; 28 <prefetch_handler>
10: e59ff014 ldr pc, [pc, #20] ; 2c <data_handler>
14: e59ff014 ldr pc, [pc, #20] ; 30 <unused_handler>
18: e59ff014 ldr pc, [pc, #20] ; 34 <irq_handler>
1c: e59ff014 ldr pc, [pc, #20] ; 38 <fiq_handler>
00000020 <undefined_handler>:
20: 000000ac andeq r0, r0, ip, lsr #1
00000024 <swi_handler>:
24: 000000ac andeq r0, r0, ip, lsr #1
00000028 <prefetch_handler>:
28: 000000ac andeq r0, r0, ip, lsr #1
0000002c <data_handler>:
2c: 000000ac andeq r0, r0, ip, lsr #1
00000030 <unused_handler>:
30: 000000ac andeq r0, r0, ip, lsr #1
00000034 <irq_handler>:
34: 000000d4 ldrdeq r0, [r0], -r4
00000038 <fiq_handler>:
38: 000000ac andeq r0, r0, ip, lsr #1
0000003c <text_size_x>:
3c: 00000304 andeq r0, r0, r4, lsl #6
00000040 <soffset>:
40: 0000004c andeq r0, r0, ip, asr #32
00000044 <reset>:
44: e1a0000f mov r0, pc
48: e51f1010 ldr r1, [pc, #-16] ; 40 <soffset>
4c: e0400001 sub r0, r0, r1
50: e3500000 cmp r0, #0
54: 0a00000a beq 84 <skip_copy>
58: e3a01000 mov r1, #0
5c: e51f2028 ldr r2, [pc, #-40] ; 3c <text_size_x>
60: e28220ff add r2, r2, #255 ; 0xff
64: e282200f add r2, r2, #15
68: e1a02222 lsr r2, r2, #4
0000006c <copy_loop>:
6c: e8b000f0 ldm r0!, {r4, r5, r6, r7}
70: e8a100f0 stmia r1!, {r4, r5, r6, r7}
74: e2522001 subs r2, r2, #1
78: 1afffffb bne 6c <copy_loop>
7c: e3a00000 mov r0, #0
80: e12fff10 bx r0
00000084 <skip_copy>:
84: e3a000d2 mov r0, #210 ; 0xd2
88: e121f000 msr CPSR_c, r0
8c: e3a0d406 mov sp, #100663296 ; 0x6000000
90: e3a000d1 mov r0, #209 ; 0xd1
94: e121f000 msr CPSR_c, r0
98: e3a0d407 mov sp, #117440512 ; 0x7000000
9c: e3a000d3 mov r0, #211 ; 0xd3
a0: e121f000 msr CPSR_c, r0
a4: e3a0d302 mov sp, #134217728 ; 0x8000000
a8: eb000021 bl 134 <notmain>
000000ac <hang>:
ac: eafffffe b ac <hang>
000000b0 <PUT32>:
b0: e5801000 str r1, [r0]
b4: e12fff1e bx lr
000000b8 <GET32>:
b8: e5900000 ldr r0, [r0]
bc: e12fff1e bx lr
000000c0 <dummy>:
c0: e12fff1e bx lr
000000c4 <enable_irq>:
c4: e10f0000 mrs r0, CPSR
c8: e3c00080 bic r0, r0, #128 ; 0x80
cc: e121f000 msr CPSR_c, r0
d0: e12fff1e bx lr
000000d4 <irq>:
d4: e92d5fff push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
d8: eb000001 bl e4 <c_irq_handler>
dc: e8bd5fff pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
e0: e25ef004 subs pc, lr, #4
000000e4 <c_irq_handler>:
e4: e59f1038 ldr r1, [pc, #56] ; 124 <c_irq_handler+0x40>
e8: e591c000 ldr ip, [r1]
ec: e28c2001 add r2, ip, #1
f0: e92d4008 push {r3, lr}
f4: e5812000 str r2, [r1]
f8: e5913000 ldr r3, [r1]
fc: e3130001 tst r3, #1
100: 159f0020 ldrne r0, [pc, #32] ; 128 <c_irq_handler+0x44>
104: 059f0020 ldreq r0, [pc, #32] ; 12c <c_irq_handler+0x48>
108: e3a01801 mov r1, #65536 ; 0x10000
10c: ebffffe7 bl b0 <PUT32>
110: e59f0018 ldr r0, [pc, #24] ; 130 <c_irq_handler+0x4c>
114: e3a01000 mov r1, #0
118: ebffffe4 bl b0 <PUT32>
11c: e8bd4008 pop {r3, lr}
120: e12fff1e bx lr
124: 00000304 andeq r0, r0, r4, lsl #6
128: 20200028 eorcs r0, r0, r8, lsr #32
12c: 2020001c eorcs r0, r0, ip, lsl r0
130: 2000b40c andcs fp, r0, ip, lsl #8
00000134 <notmain>:
134: e92d4010 push {r4, lr}
138: e3a01001 mov r1, #1
13c: e59f017c ldr r0, [pc, #380] ; 2c0 <notmain+0x18c>
140: ebffffda bl b0 <PUT32>
144: e59f0178 ldr r0, [pc, #376] ; 2c4 <notmain+0x190>
148: ebffffda bl b8 <GET32>
14c: e3c01707 bic r1, r0, #1835008 ; 0x1c0000
150: e3811701 orr r1, r1, #262144 ; 0x40000
154: e59f0168 ldr r0, [pc, #360] ; 2c4 <notmain+0x190>
158: ebffffd4 bl b0 <PUT32>
15c: e59f0164 ldr r0, [pc, #356] ; 2c8 <notmain+0x194>
160: e3a01801 mov r1, #65536 ; 0x10000
164: ebffffd1 bl b0 <PUT32>
168: e59f015c ldr r0, [pc, #348] ; 2cc <notmain+0x198>
16c: e3a0183e mov r1, #4063232 ; 0x3e0000
170: ebffffce bl b0 <PUT32>
174: e59f0154 ldr r0, [pc, #340] ; 2d0 <notmain+0x19c>
178: e59f1154 ldr r1, [pc, #340] ; 2d4 <notmain+0x1a0>
17c: ebffffcb bl b0 <PUT32>
180: e59f0150 ldr r0, [pc, #336] ; 2d8 <notmain+0x1a4>
184: e59f1148 ldr r1, [pc, #328] ; 2d4 <notmain+0x1a0>
188: ebffffc8 bl b0 <PUT32>
18c: e59f0148 ldr r0, [pc, #328] ; 2dc <notmain+0x1a8>
190: e3a010f9 mov r1, #249 ; 0xf9
194: ebffffc5 bl b0 <PUT32>
198: e59f0140 ldr r0, [pc, #320] ; 2e0 <notmain+0x1ac>
19c: e3a01000 mov r1, #0
1a0: ebffffc2 bl b0 <PUT32>
1a4: e59f0120 ldr r0, [pc, #288] ; 2cc <notmain+0x198>
1a8: e59f1134 ldr r1, [pc, #308] ; 2e4 <notmain+0x1b0>
1ac: ebffffbf bl b0 <PUT32>
1b0: e3a04005 mov r4, #5
1b4: e59f012c ldr r0, [pc, #300] ; 2e8 <notmain+0x1b4>
1b8: e3a01801 mov r1, #65536 ; 0x10000
1bc: ebffffbb bl b0 <PUT32>
1c0: e59f0124 ldr r0, [pc, #292] ; 2ec <notmain+0x1b8>
1c4: ebffffbb bl b8 <GET32>
1c8: e3500000 cmp r0, #0
1cc: 0afffffb beq 1c0 <notmain+0x8c>
1d0: e59f0108 ldr r0, [pc, #264] ; 2e0 <notmain+0x1ac>
1d4: e3a01000 mov r1, #0
1d8: ebffffb4 bl b0 <PUT32>
1dc: e59f00e4 ldr r0, [pc, #228] ; 2c8 <notmain+0x194>
1e0: e3a01801 mov r1, #65536 ; 0x10000
1e4: ebffffb1 bl b0 <PUT32>
1e8: e59f00fc ldr r0, [pc, #252] ; 2ec <notmain+0x1b8>
1ec: ebffffb1 bl b8 <GET32>
1f0: e3500000 cmp r0, #0
1f4: 0afffffb beq 1e8 <notmain+0xb4>
1f8: e59f00e0 ldr r0, [pc, #224] ; 2e0 <notmain+0x1ac>
1fc: e3a01000 mov r1, #0
200: ebffffaa bl b0 <PUT32>
204: e2544001 subs r4, r4, #1
208: 1affffe9 bne 1b4 <notmain+0x80>
20c: e59f00bc ldr r0, [pc, #188] ; 2d0 <notmain+0x19c>
210: e59f10d8 ldr r1, [pc, #216] ; 2f0 <notmain+0x1bc>
214: ebffffa5 bl b0 <PUT32>
218: e59f00b8 ldr r0, [pc, #184] ; 2d8 <notmain+0x1a4>
21c: e59f10cc ldr r1, [pc, #204] ; 2f0 <notmain+0x1bc>
220: ebffffa2 bl b0 <PUT32>
224: e1a01004 mov r1, r4
228: e59f00b0 ldr r0, [pc, #176] ; 2e0 <notmain+0x1ac>
22c: ebffff9f bl b0 <PUT32>
230: e59f00bc ldr r0, [pc, #188] ; 2f4 <notmain+0x1c0>
234: e3a01001 mov r1, #1
238: ebffff9c bl b0 <PUT32>
23c: e3a04005 mov r4, #5
240: e59f00a0 ldr r0, [pc, #160] ; 2e8 <notmain+0x1b4>
244: e3a01801 mov r1, #65536 ; 0x10000
248: ebffff98 bl b0 <PUT32>
24c: e59f00a4 ldr r0, [pc, #164] ; 2f8 <notmain+0x1c4>
250: ebffff98 bl b8 <GET32>
254: e3100001 tst r0, #1
258: 0afffffb beq 24c <notmain+0x118>
25c: e59f007c ldr r0, [pc, #124] ; 2e0 <notmain+0x1ac>
260: e3a01000 mov r1, #0
264: ebffff91 bl b0 <PUT32>
268: e59f0058 ldr r0, [pc, #88] ; 2c8 <notmain+0x194>
26c: e3a01801 mov r1, #65536 ; 0x10000
270: ebffff8e bl b0 <PUT32>
274: e59f007c ldr r0, [pc, #124] ; 2f8 <notmain+0x1c4>
278: ebffff8e bl b8 <GET32>
27c: e3100001 tst r0, #1
280: 0afffffb beq 274 <notmain+0x140>
284: e59f0054 ldr r0, [pc, #84] ; 2e0 <notmain+0x1ac>
288: e3a01000 mov r1, #0
28c: ebffff87 bl b0 <PUT32>
290: e2544001 subs r4, r4, #1
294: 1affffe9 bne 240 <notmain+0x10c>
298: e59f0030 ldr r0, [pc, #48] ; 2d0 <notmain+0x19c>
29c: e59f1058 ldr r1, [pc, #88] ; 2fc <notmain+0x1c8>
2a0: ebffff82 bl b0 <PUT32>
2a4: e59f002c ldr r0, [pc, #44] ; 2d8 <notmain+0x1a4>
2a8: e59f104c ldr r1, [pc, #76] ; 2fc <notmain+0x1c8>
2ac: ebffff7f bl b0 <PUT32>
2b0: e59f3048 ldr r3, [pc, #72] ; 300 <notmain+0x1cc>
2b4: e5834000 str r4, [r3]
2b8: ebffff81 bl c4 <enable_irq>
2bc: eafffffe b 2bc <notmain+0x188>
2c0: 2000b224 andcs fp, r0, r4, lsr #4
2c4: 20200004 eorcs r0, r0, r4
2c8: 2020001c eorcs r0, r0, ip, lsl r0
2cc: 2000b408 andcs fp, r0, r8, lsl #8
2d0: 2000b400 andcs fp, r0, r0, lsl #8
2d4: 000f423f andeq r4, pc, pc, lsr r2 ; <UNPREDICTABLE>
2d8: 2000b418 andcs fp, r0, r8, lsl r4
2dc: 2000b41c andcs fp, r0, ip, lsl r4
2e0: 2000b40c andcs fp, r0, ip, lsl #8
2e4: 003e00a2 eorseq r0, lr, r2, lsr #1
2e8: 20200028 eorcs r0, r0, r8, lsr #32
2ec: 2000b414 andcs fp, r0, r4, lsl r4
2f0: 001e847f andseq r8, lr, pc, ror r4
2f4: 2000b218 andcs fp, r0, r8, lsl r2
2f8: 2000b200 andcs fp, r0, r0, lsl #4
2fc: 003d08ff ldrshteq r0, [sp], -pc
300: 00000304 andeq r0, r0, r4, lsl #6
Disassembly of section .bss:
00000304 <icount>:
304: 00000000 andeq r0, r0, r0
Disassembly of section .ARM.attributes:
00000000 <.ARM.attributes>:
0: 00002c41 andeq r2, r0, r1, asr #24
4: 61656100 cmnvs r5, r0, lsl #2
8: 01006962 tsteq r0, r2, ror #18
c: 00000022 andeq r0, r0, r2, lsr #32
10: 4d524105 ldfmie f4, [r2, #-20] ; 0xffffffec
14: 54347620 ldrtpl r7, [r4], #-1568 ; 0xfffff9e0
18: 08020600 stmdaeq r2, {r9, sl}
1c: 12010901 andne r0, r1, #16384 ; 0x4000
20: 15011404 strne r1, [r1, #-1028] ; 0xfffffbfc
24: 18031701 stmdane r3, {r0, r8, r9, sl, ip}
28: 2c011a01 stccs 10, cr1, [r1], {1}
2c: Address 0x0000002c is out of bounds.
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 bcc 10d0d24 <text_size+0x10d0a20>
4: 6f532820 svcvs 0x00532820
8: 65637275 strbvs r7, [r3, #-629]! ; 0xfffffd8b
c: 43207972 teqmi r0, #1867776 ; 0x1c8000
10: 4265646f rsbmi r6, r5, #1862270976 ; 0x6f000000
14: 68636e65 stmdavs r3!, {r0, r2, r5, r6, r9, sl, fp, sp, lr}^
18: 74694c20 strbtvc r4, [r9], #-3104 ; 0xfffff3e0
1c: 30322065 eorscc r2, r2, r5, rrx
20: 302e3131 eorcc r3, lr, r1, lsr r1
24: 39362d39 ldmdbcc r6!, {r0, r3, r4, r5, r8, sl, fp, sp}
28: 2e342029 cdpcs 0, 3, cr2, cr4, cr9, {1}
2c: 00312e36 eorseq r2, r1, r6, lsr lr

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;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
.globl _start
_start:
b reset
ldr pc,undefined_handler
ldr pc,swi_handler
ldr pc,prefetch_handler
ldr pc,data_handler
ldr pc,unused_handler
ldr pc,irq_handler
ldr pc,fiq_handler
undefined_handler: .word hang
swi_handler: .word hang
prefetch_handler: .word hang
data_handler: .word hang
unused_handler: .word hang
irq_handler: .word irq
fiq_handler: .word hang
text_size_x: .word text_size
soffset: .word reset - _start + 8
reset:
mov r0,pc
ldr r1,soffset
sub r0,r1
cmp r0,#0
beq skip_copy
mov r1,#0;
ldr r2,text_size_x
add r2,r2,#0xFF
add r2,r2,#15
mov r2,r2,lsr #4
copy_loop:
ldmia r0!,{r4,r5,r6,r7}
stmia r1!,{r4,r5,r6,r7}
subs r2,r2,#1
bne copy_loop
mov r0,#0
bx r0
skip_copy:
;@ (PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
mov r0,#0xD2
msr cpsr_c,r0
mov sp,#0x6000000
;@ (PSR_FIQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
mov r0,#0xD1
msr cpsr_c,r0
mov sp,#0x7000000
;@ (PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
mov r0,#0xD3
msr cpsr_c,r0
mov sp,#0x8000000
;@ SVC MODE, IRQ ENABLED, FIQ DIS
;@mov r0,#0x53
;@msr cpsr_c, r0
bl notmain
hang: b hang
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl dummy
dummy:
bx lr
.globl enable_irq
enable_irq:
mrs r0,cpsr
bic r0,r0,#0x80
msr cpsr_c,r0
bx lr
irq:
push {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
bl c_irq_handler
pop {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
subs pc,lr,#4
;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
;@
;@ Copyright (c) 2012 David Welch dwelch@dwelch.com
;@
;@ Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
;@
;@ The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;@
;@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;@
;@-------------------------------------------------------------------------

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MEMORY
{
ram : ORIGIN = 0x0000, LENGTH = 0x1000
}
SECTIONS
{
.text : { *(.text*) } > ram
text_size = SIZEOF(.text);
.bss : { *(.bss*) } > ram
}

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//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
extern void PUT32 ( unsigned int, unsigned int );
extern unsigned int GET32 ( unsigned int );
extern void dummy ( unsigned int );
#define GPFSEL1 0x20200004
#define GPSET0 0x2020001C
#define GPCLR0 0x20200028
#define GPPUD 0x20200094
#define GPPUDCLK0 0x20200098
#define AUX_ENABLES 0x20215004
#define AUX_MU_IO_REG 0x20215040
#define AUX_MU_IER_REG 0x20215044
#define AUX_MU_IIR_REG 0x20215048
#define AUX_MU_LCR_REG 0x2021504C
#define AUX_MU_MCR_REG 0x20215050
#define AUX_MU_LSR_REG 0x20215054
#define AUX_MU_MSR_REG 0x20215058
#define AUX_MU_SCRATCH 0x2021505C
#define AUX_MU_CNTL_REG 0x20215060
#define AUX_MU_STAT_REG 0x20215064
#define AUX_MU_BAUD_REG 0x20215068
//GPIO14 TXD0 and TXD1
//GPIO15 RXD0 and RXD1
//alt function 5 for uart1
//alt function 0 for uart0
//((250,000,000/115200)/8)-1 = 270
//------------------------------------------------------------------------
void uart_putc ( unsigned int c )
{
while(1)
{
if(GET32(AUX_MU_LSR_REG)&0x20) break;
}
PUT32(AUX_MU_IO_REG,c);
}
//------------------------------------------------------------------------
void hexstrings ( unsigned int d )
{
//unsigned int ra;
unsigned int rb;
unsigned int rc;
rb=32;
while(1)
{
rb-=4;
rc=(d>>rb)&0xF;
if(rc>9) rc+=0x37; else rc+=0x30;
uart_putc(rc);
if(rb==0) break;
}
uart_putc(0x20);
}
//------------------------------------------------------------------------
void hexstring ( unsigned int d )
{
hexstrings(d);
uart_putc(0x0D);
uart_putc(0x0A);
}
//------------------------------------------------------------------------
int notmain ( unsigned int earlypc )
{
unsigned int ra;
PUT32(AUX_ENABLES,1);
PUT32(AUX_MU_IER_REG,0);
PUT32(AUX_MU_CNTL_REG,0);
PUT32(AUX_MU_LCR_REG,3);
PUT32(AUX_MU_MCR_REG,0);
PUT32(AUX_MU_IER_REG,0);
PUT32(AUX_MU_IIR_REG,0xC6);
PUT32(AUX_MU_BAUD_REG,270);
ra=GET32(GPFSEL1);
ra&=~(7<<12); //gpio14
ra|=2<<12; //alt5
ra&=~(7<<15); //gpio15
ra|=2<<15; //alt5
PUT32(GPFSEL1,ra);
PUT32(GPPUD,0);
for(ra=0;ra<150;ra++) dummy(ra);
PUT32(GPPUDCLK0,(1<<14)|(1<<15));
for(ra=0;ra<150;ra++) dummy(ra);
PUT32(GPPUDCLK0,0);
PUT32(AUX_MU_CNTL_REG,3);
hexstring(0x12345678);
hexstring(earlypc);
while(1)
{
while(1)
{
if(GET32(AUX_MU_LSR_REG)&0x01) break;
}
ra=GET32(AUX_MU_IO_REG);
//while(1)
//{
//if(GET32(AUX_MU_LSR_REG)&0x20) break;
//}
PUT32(AUX_MU_IO_REG,ra);
}
return(0);
}
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//
// Copyright (c) 2012 David Welch dwelch@dwelch.com
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//-------------------------------------------------------------------------

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uart02.elf: file format elf32-littlearm
Disassembly of section .text:
00000000 <_start>:
0: ea000008 b 28 <reset>
4: ea000007 b 28 <reset>
8: ea000006 b 28 <reset>
c: ea000005 b 28 <reset>
10: ea000004 b 28 <reset>
14: ea000003 b 28 <reset>
18: ea000002 b 28 <reset>
1c: ea000001 b 28 <reset>
00000020 <text_size_x>:
20: 00000310 andeq r0, r0, r0, lsl r3
00000024 <soffset>:
24: 00000030 andeq r0, r0, r0, lsr r0
00000028 <reset>:
28: e1a0000f mov r0, pc
2c: e51f1010 ldr r1, [pc, #-16] ; 24 <soffset>
30: e0400001 sub r0, r0, r1
34: e3500000 cmp r0, #0
38: 0a00000a beq 68 <skip_copy>
3c: e3a01000 mov r1, #0
40: e51f2028 ldr r2, [pc, #-40] ; 20 <text_size_x>
44: e28220ff add r2, r2, #255 ; 0xff
48: e282200f add r2, r2, #15
4c: e1a02222 lsr r2, r2, #4
00000050 <copy_loop>:
50: e8b000f0 ldm r0!, {r4, r5, r6, r7}
54: e8a100f0 stmia r1!, {r4, r5, r6, r7}
58: e2522001 subs r2, r2, #1
5c: 1afffffb bne 50 <copy_loop>
60: e3a00000 mov r0, #0
64: e12fff10 bx r0
00000068 <skip_copy>:
68: e3a0d902 mov sp, #32768 ; 0x8000
6c: e1a0000f mov r0, pc
70: eb00004c bl 1a8 <notmain>
00000074 <hang>:
74: eafffffe b 74 <hang>
00000078 <PUT32>:
78: e5801000 str r1, [r0]
7c: e12fff1e bx lr
00000080 <GET32>:
80: e5900000 ldr r0, [r0]
84: e12fff1e bx lr
00000088 <dummy>:
88: e12fff1e bx lr
0000008c <uart_putc>:
8c: e92d4010 push {r4, lr}
90: e1a04000 mov r4, r0
94: e59f001c ldr r0, [pc, #28] ; b8 <uart_putc+0x2c>
98: ebfffff8 bl 80 <GET32>
9c: e3100020 tst r0, #32
a0: 0afffffb beq 94 <uart_putc+0x8>
a4: e59f0010 ldr r0, [pc, #16] ; bc <uart_putc+0x30>
a8: e1a01004 mov r1, r4
ac: ebfffff1 bl 78 <PUT32>
b0: e8bd4010 pop {r4, lr}
b4: e12fff1e bx lr
b8: 20215054 eorcs r5, r1, r4, asr r0
bc: 20215040 eorcs r5, r1, r0, asr #32
000000c0 <hexstrings>:
c0: e92d4010 push {r4, lr}
c4: e1a04000 mov r4, r0
c8: e1a00e20 lsr r0, r0, #28
cc: e3500009 cmp r0, #9
d0: 92800030 addls r0, r0, #48 ; 0x30
d4: 82800037 addhi r0, r0, #55 ; 0x37
d8: ebffffeb bl 8c <uart_putc>
dc: e1a00c24 lsr r0, r4, #24
e0: e200000f and r0, r0, #15
e4: e3500009 cmp r0, #9
e8: 92800030 addls r0, r0, #48 ; 0x30
ec: 82800037 addhi r0, r0, #55 ; 0x37
f0: ebffffe5 bl 8c <uart_putc>
f4: e1a0ca24 lsr ip, r4, #20
f8: e20c000f and r0, ip, #15
fc: e3500009 cmp r0, #9
100: 92800030 addls r0, r0, #48 ; 0x30
104: 82800037 addhi r0, r0, #55 ; 0x37
108: ebffffdf bl 8c <uart_putc>
10c: e1a03824 lsr r3, r4, #16
110: e203000f and r0, r3, #15
114: e3500009 cmp r0, #9
118: 92800030 addls r0, r0, #48 ; 0x30
11c: 82800037 addhi r0, r0, #55 ; 0x37
120: ebffffd9 bl 8c <uart_putc>
124: e1a02624 lsr r2, r4, #12
128: e202000f and r0, r2, #15
12c: e3500009 cmp r0, #9
130: 92800030 addls r0, r0, #48 ; 0x30
134: 82800037 addhi r0, r0, #55 ; 0x37
138: ebffffd3 bl 8c <uart_putc>
13c: e1a01424 lsr r1, r4, #8
140: e201000f and r0, r1, #15
144: e3500009 cmp r0, #9
148: 92800030 addls r0, r0, #48 ; 0x30
14c: 82800037 addhi r0, r0, #55 ; 0x37
150: ebffffcd bl 8c <uart_putc>
154: e1a00224 lsr r0, r4, #4
158: e200000f and r0, r0, #15
15c: e3500009 cmp r0, #9
160: 92800030 addls r0, r0, #48 ; 0x30
164: 82800037 addhi r0, r0, #55 ; 0x37
168: e204400f and r4, r4, #15
16c: ebffffc6 bl 8c <uart_putc>
170: e3540009 cmp r4, #9
174: 82840037 addhi r0, r4, #55 ; 0x37
178: 92840030 addls r0, r4, #48 ; 0x30
17c: ebffffc2 bl 8c <uart_putc>
180: e3a00020 mov r0, #32
184: e8bd4010 pop {r4, lr}
188: eaffffbf b 8c <uart_putc>
0000018c <hexstring>:
18c: e92d4008 push {r3, lr}
190: ebffffca bl c0 <hexstrings>
194: e3a0000d mov r0, #13
198: ebffffbb bl 8c <uart_putc>
19c: e3a0000a mov r0, #10
1a0: e8bd4008 pop {r3, lr}
1a4: eaffffb8 b 8c <uart_putc>
000001a8 <notmain>:
1a8: e92d4070 push {r4, r5, r6, lr}
1ac: e3a01001 mov r1, #1
1b0: e1a04000 mov r4, r0
1b4: e59f011c ldr r0, [pc, #284] ; 2d8 <notmain+0x130>
1b8: ebffffae bl 78 <PUT32>
1bc: e59f0118 ldr r0, [pc, #280] ; 2dc <notmain+0x134>
1c0: e3a01000 mov r1, #0
1c4: ebffffab bl 78 <PUT32>
1c8: e59f0110 ldr r0, [pc, #272] ; 2e0 <notmain+0x138>
1cc: e3a01000 mov r1, #0
1d0: ebffffa8 bl 78 <PUT32>
1d4: e59f0108 ldr r0, [pc, #264] ; 2e4 <notmain+0x13c>
1d8: e3a01003 mov r1, #3
1dc: ebffffa5 bl 78 <PUT32>
1e0: e59f0100 ldr r0, [pc, #256] ; 2e8 <notmain+0x140>
1e4: e3a01000 mov r1, #0
1e8: ebffffa2 bl 78 <PUT32>
1ec: e59f00e8 ldr r0, [pc, #232] ; 2dc <notmain+0x134>
1f0: e3a01000 mov r1, #0
1f4: ebffff9f bl 78 <PUT32>
1f8: e59f00ec ldr r0, [pc, #236] ; 2ec <notmain+0x144>
1fc: e3a010c6 mov r1, #198 ; 0xc6
200: ebffff9c bl 78 <PUT32>
204: e59f10e4 ldr r1, [pc, #228] ; 2f0 <notmain+0x148>
208: e59f00e4 ldr r0, [pc, #228] ; 2f4 <notmain+0x14c>
20c: ebffff99 bl 78 <PUT32>
210: e59f00e0 ldr r0, [pc, #224] ; 2f8 <notmain+0x150>
214: ebffff99 bl 80 <GET32>
218: e3c01a3f bic r1, r0, #258048 ; 0x3f000
21c: e3811a12 orr r1, r1, #73728 ; 0x12000
220: e59f00d0 ldr r0, [pc, #208] ; 2f8 <notmain+0x150>
224: ebffff93 bl 78 <PUT32>
228: e59f00cc ldr r0, [pc, #204] ; 2fc <notmain+0x154>
22c: e3a01000 mov r1, #0
230: ebffff90 bl 78 <PUT32>
234: e3a05000 mov r5, #0
238: e1a00005 mov r0, r5
23c: e2856001 add r6, r5, #1
240: ebffff90 bl 88 <dummy>
244: e2855002 add r5, r5, #2
248: e1a00006 mov r0, r6
24c: ebffff8d bl 88 <dummy>
250: e3550096 cmp r5, #150 ; 0x96
254: 1afffff7 bne 238 <notmain+0x90>
258: e59f00a0 ldr r0, [pc, #160] ; 300 <notmain+0x158>
25c: e3a01903 mov r1, #49152 ; 0xc000
260: ebffff84 bl 78 <PUT32>
264: e3a05000 mov r5, #0
268: e1a00005 mov r0, r5
26c: e2856001 add r6, r5, #1
270: ebffff84 bl 88 <dummy>
274: e2855002 add r5, r5, #2
278: e1a00006 mov r0, r6
27c: ebffff81 bl 88 <dummy>
280: e3550096 cmp r5, #150 ; 0x96
284: 1afffff7 bne 268 <notmain+0xc0>
288: e59f0070 ldr r0, [pc, #112] ; 300 <notmain+0x158>
28c: e3a01000 mov r1, #0
290: ebffff78 bl 78 <PUT32>
294: e59f0044 ldr r0, [pc, #68] ; 2e0 <notmain+0x138>
298: e3a01003 mov r1, #3
29c: ebffff75 bl 78 <PUT32>
2a0: e59f005c ldr r0, [pc, #92] ; 304 <notmain+0x15c>
2a4: ebffffb8 bl 18c <hexstring>
2a8: e1a00004 mov r0, r4
2ac: ebffffb6 bl 18c <hexstring>
2b0: e59f0050 ldr r0, [pc, #80] ; 308 <notmain+0x160>
2b4: ebffff71 bl 80 <GET32>
2b8: e3100001 tst r0, #1
2bc: 0afffffb beq 2b0 <notmain+0x108>
2c0: e59f0044 ldr r0, [pc, #68] ; 30c <notmain+0x164>
2c4: ebffff6d bl 80 <GET32>
2c8: e1a01000 mov r1, r0
2cc: e59f0038 ldr r0, [pc, #56] ; 30c <notmain+0x164>
2d0: ebffff68 bl 78 <PUT32>
2d4: eafffff5 b 2b0 <notmain+0x108>
2d8: 20215004 eorcs r5, r1, r4
2dc: 20215044 eorcs r5, r1, r4, asr #32
2e0: 20215060 eorcs r5, r1, r0, rrx
2e4: 2021504c eorcs r5, r1, ip, asr #32
2e8: 20215050 eorcs r5, r1, r0, asr r0
2ec: 20215048 eorcs r5, r1, r8, asr #32
2f0: 0000010e andeq r0, r0, lr, lsl #2
2f4: 20215068 eorcs r5, r1, r8, rrx
2f8: 20200004 eorcs r0, r0, r4
2fc: 20200094 mlacs r0, r4, r0, r0
300: 20200098 mlacs r0, r8, r0, r0
304: 12345678 eorsne r5, r4, #120, 12 ; 0x7800000
308: 20215054 eorcs r5, r1, r4, asr r0
30c: 20215040 eorcs r5, r1, r0, asr #32
Disassembly of section .ARM.attributes:
00000000 <.ARM.attributes>:
0: 00002c41 andeq r2, r0, r1, asr #24
4: 61656100 cmnvs r5, r0, lsl #2
8: 01006962 tsteq r0, r2, ror #18
c: 00000022 andeq r0, r0, r2, lsr #32
10: 4d524105 ldfmie f4, [r2, #-20] ; 0xffffffec
14: 54347620 ldrtpl r7, [r4], #-1568 ; 0xfffff9e0
18: 08020600 stmdaeq r2, {r9, sl}
1c: 12010901 andne r0, r1, #16384 ; 0x4000
20: 15011404 strne r1, [r1, #-1028] ; 0xfffffbfc
24: 18031701 stmdane r3, {r0, r8, r9, sl, ip}
28: 2c011a01 stccs 10, cr1, [r1], {1}
2c: Address 0x0000002c is out of bounds.
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 bcc 10d0d24 <text_size+0x10d0a14>
4: 6f532820 svcvs 0x00532820
8: 65637275 strbvs r7, [r3, #-629]! ; 0xfffffd8b
c: 43207972 teqmi r0, #1867776 ; 0x1c8000
10: 4265646f rsbmi r6, r5, #1862270976 ; 0x6f000000
14: 68636e65 stmdavs r3!, {r0, r2, r5, r6, r9, sl, fp, sp, lr}^
18: 74694c20 strbtvc r4, [r9], #-3104 ; 0xfffff3e0
1c: 30322065 eorscc r2, r2, r5, rrx
20: 302e3131 eorcc r3, lr, r1, lsr r1
24: 39362d39 ldmdbcc r6!, {r0, r3, r4, r5, r8, sl, fp, sp}
28: 2e342029 cdpcs 0, 3, cr2, cr4, cr9, {1}
2c: 00312e36 eorseq r2, r1, r6, lsr lr

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.globl _start
_start:
b reset
b reset
b reset
b reset
b reset
b reset
b reset
b reset
text_size_x: .word text_size
soffset: .word reset - _start + 8
reset:
mov r0,pc
ldr r1,soffset
sub r0,r1
cmp r0,#0
beq skip_copy
mov r1,#0;
ldr r2,text_size_x
add r2,r2,#0xFF
add r2,r2,#15
mov r2,r2,lsr #4
copy_loop:
ldmia r0!,{r4,r5,r6,r7}
stmia r1!,{r4,r5,r6,r7}
subs r2,r2,#1
bne copy_loop
mov r0,#0
bx r0
skip_copy:
mov sp,#0x8000
mov r0,pc
bl notmain
hang: b hang
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl dummy
dummy:
bx lr
;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
;@
;@ Copyright (c) 2012 David Welch dwelch@dwelch.com
;@
;@ Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
;@
;@ The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;@
;@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;@
;@-------------------------------------------------------------------------