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Merge pull request #1 from igor-m/master

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Fubarino and new rd_sramc driver related changes
This commit is contained in:
Matt Jenkins
2014-04-10 23:43:51 +01:00
parent 5ef98b2b76 b9fa96f8bc
commit bd4d40ad3e
14 changed files with 395 additions and 543 deletions
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14
Makefile
View File

@@ -26,9 +26,9 @@ DUINOMITEEUART = sys/pic32/duinomite-e-uart/DUINOMITE-E-UART
PINGUINO = sys/pic32/pinguino-micro/PINGUINO-MICRO
DIP = sys/pic32/dip/DIP
BAREMETAL = sys/pic32/baremetal/BAREMETAL
RETROONE = sys/pic32/retroone/RETROONE
FUBARINO = sys/pic32/fubarino/FUBARINO
FUBARINOUART = sys/pic32/fubarino-uart/FUBARINO-UART
RETROONE = sys/pic32/retroone/RETROONE
FUBARINO = sys/pic32/fubarino/FUBARINO
FUBARINOBIG = sys/pic32/fubarino/FUBARINO-UART2CONS-UART1-SRAMC
MMBMX7 = sys/pic32/mmb-mx7/MMB-MX7
# Select target board
@@ -192,5 +192,13 @@ else
@echo "Error: No SDCARD defined."
endif
# TODO: make it relative to Target
installflash:
sudo pic32prog sys/pic32/fubarino/unix.hex
# TODO: make it relative to Target
installboot:
sudo pic32prog sys/pic32/fubarino/bootloader.hex
.profile: etc/root/dot.profile
cp etc/root/dot.profile .profile

45
sys/pic32/32mxsdram-uart/32MXSDRAM-UART Normal file
View File

@@ -0,0 +1,45 @@
#
# 32MXSDRAM board PCB v1.0 with UART console
# ===========================================
#
# Console on UART3
core pic32mx7
linker bootloader-sdram
mapping generic
device kernel cpu_khz=80000 bus_khz=80000 led=A15
device console led=A14 device=tty2
device uart3 baud=115200
device rdisk led=C13 swap=C14
option nproc=20
option hz=1000
# sdcard's definition for the SPI port, sdcard's chipselect and high-side power switch
# because of a mod on the board we use power=B13, otherwise it shall be D12
device sd0 port=4 cs=F3 power=B13 mhz=13
# device sd1 port=4 cs=F8 power=D13
device adc
device oc
device gpio
# use SDRAM driver for the external ramdisk
device sdramp
# This defines the swap size and a fs partition size on the external ramdisk.
# When the sa@XXXX is larger than the SWAP_KBYTES, the system will use
# the swap located on the external ramdisk automatically.
# (sd@xxxx + fs@xxxx) <= ramdisk_size
option PARTITION=sdramp0:sa@2048,fs@14000
option nmount=3
# set=pin means the pin will be set high during bootloading
device bootloader button=C1 user=0x1d005000 led=C13 led2=C14
option crystal=12
option pllidiv=3
option pllmul=20
option upllidiv=3

95
sys/pic32/32mxsdram-uart/Makefile Normal file
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@@ -0,0 +1,95 @@
BUILDPATH = ../../../tools/configsys/../../sys/pic32
H = ../../../tools/configsys/../../sys/include
M = ../../../tools/configsys/../../sys/pic32
S = ../../../tools/configsys/../../sys/kernel
vpath %.c $(M):$(S)
vpath %.S $(M):$(S)
KERNOBJ += _startup.o adc.o clock.o cons.o devsw.o exception.o gpio.o init_main.o init_sysent.o kern_clock.o kern_descrip.o kern_exec.o kern_exit.o kern_fork.o kern_mman.o kern_proc.o kern_prot.o kern_prot2.o kern_resource.o kern_sig.o kern_sig2.o kern_subr.o kern_synch.o kern_sysctl.o kern_time.o machdep.o mem.o oc.o rd_sd.o rd_sdramp.o rdisk.o sdram.o signal.o spi_bus.o subr_prf.o subr_rmap.o swap.o sys_generic.o sys_inode.o sys_pipe.o sys_process.o syscalls.o sysctl.o tty.o tty_subr.o tty_tty.o uart.o ufs_alloc.o ufs_bio.o ufs_bmap.o ufs_dsort.o ufs_fio.o ufs_inode.o ufs_mount.o ufs_namei.o ufs_subr.o ufs_syscalls.o ufs_syscalls2.o vers.o vfs_vnops.o vm_sched.o vm_swap.o vm_swp.o
EXTRA_TARGETS = bootloader
DEFS += -DADC_ENABLED=YES
DEFS += -DBL_BUTTON_PIN=1
DEFS += -DBL_BUTTON_PORT=TRISC
DEFS += -DBL_LED2_PIN=14
DEFS += -DBL_LED2_PORT=TRISC
DEFS += -DBL_LED_PIN=13
DEFS += -DBL_LED_PORT=TRISC
DEFS += -DBUS_DIV=1
DEFS += -DBUS_KHZ=80000
DEFS += -DCONSOLE_DEVICE=tty2
DEFS += -DCPU_IDIV=3
DEFS += -DCPU_KHZ=80000
DEFS += -DCPU_MUL=20
DEFS += -DCPU_ODIV=1
DEFS += -DCRYSTAL=12
DEFS += -DDC0_DEBUG=DEVCFG0_DEBUG_DISABLED
DEFS += -DDC0_ICE=0
DEFS += -DDC1_CKM=0
DEFS += -DDC1_CKS=0
DEFS += -DDC1_FNOSC=DEVCFG1_FNOSC_PRIPLL
DEFS += -DDC1_IESO=DEVCFG1_IESO
DEFS += -DDC1_OSCIOFNC=0
DEFS += -DDC1_PBDIV=DEVCFG1_FPBDIV_1
DEFS += -DDC1_POSCMOD=DEVCFG1_POSCMOD_HS
DEFS += -DDC1_SOSC=0
DEFS += -DDC1_WDTEN=0
DEFS += -DDC1_WDTPS=DEVCFG1_WDTPS_1
DEFS += -DDC2_PLLIDIV=DEVCFG2_FPLLIDIV_3
DEFS += -DDC2_PLLMUL=DEVCFG2_FPLLMUL_20
DEFS += -DDC2_PLLODIV=DEVCFG2_FPLLODIV_1
DEFS += -DDC2_UPLL=0
DEFS += -DDC2_UPLLIDIV=DEVCFG2_UPLLIDIV_3
DEFS += -DDC3_CAN=DEVCFG3_FCANIO
DEFS += -DDC3_ETH=DEVCFG3_FETHIO
DEFS += -DDC3_MII=DEVCFG3_FMIIEN
DEFS += -DDC3_SRS=DEVCFG3_FSRSSEL_7
DEFS += -DDC3_USBID=DEVCFG3_FUSBIDIO
DEFS += -DDC3_USERID=0xffff
DEFS += -DDC3_VBUSON=DEVCFG3_FVBUSONIO
DEFS += -DFLASH_USER=0x1d005000
DEFS += -DGPIO_ENABLED=YES
DEFS += -DHID_FEATURE_REPORT_BYTES=2
DEFS += -DHID_INPUT_REPORT_BYTES=2
DEFS += -DHID_INT_IN_EP_SIZE=64
DEFS += -DHID_INT_OUT_EP_SIZE=64
DEFS += -DHID_OUTPUT_REPORT_BYTES=2
DEFS += -DHID_RPT01_SIZE=29
DEFS += -DHZ=1000
DEFS += -DKERNEL
DEFS += -DKERNEL_EXECUTABLE_RAM
DEFS += -DLED_DISK_PIN=13
DEFS += -DLED_DISK_PORT=TRISC
DEFS += -DLED_KERNEL_PIN=15
DEFS += -DLED_KERNEL_PORT=TRISA
DEFS += -DLED_SWAP_PIN=14
DEFS += -DLED_SWAP_PORT=TRISC
DEFS += -DLED_TTY_PIN=14
DEFS += -DLED_TTY_PORT=TRISA
DEFS += -DNMOUNT=3
DEFS += -DNPROC=20
DEFS += -DOC_ENABLED=YES
DEFS += -DPARTITION="sdramp0:sa@2048,fs@14000"
DEFS += -DPIC32MX7
DEFS += -DSD0_CS_PIN=3
DEFS += -DSD0_CS_PORT=TRISF
DEFS += -DSD0_ENA_PIN=13
DEFS += -DSD0_ENA_PORT=TRISB
DEFS += -DSD0_MHZ=13
DEFS += -DSD0_PORT=4
DEFS += -DSDRAMP_ENABLED=YES
DEFS += -DUART3_BAUD=115200
DEFS += -DUART3_ENABLED=YES
DEFS += -DUCB_METER
DEFS += -DUSB_EP0_BUFF_SIZE=8
DEFS += -DUSB_MAX_EP_NUMBER=1
DEFS += -DUSB_NUM_STRING_DESCRIPTORS=3
LDSCRIPT = ../../../tools/configsys/../../sys/pic32/cfg/bootloader-sdram.ld
CONFIG = 32MXSDRAM-UART
CONFIGPATH = ../../../tools/configsys
include ../../../tools/configsys/../../sys/pic32/kernel-post.mk

40
sys/pic32/fubarino-uart/using-bootloader.ld → sys/pic32/32mxsdram-uart/using-bootloader-ker.ld
View File

@@ -1,5 +1,5 @@
/*
* Linker script for PIC32 firmware using RetroBSD bootloader.
* Linker script for PIC32 firmware using HID bootloader.
*/
OUTPUT_FORMAT("elf32-littlemips", "elf32-bigmips",
"elf32-littlemips")
@@ -7,16 +7,17 @@ OUTPUT_ARCH(mips)
ENTRY(_reset_vector_)
MEMORY
{
flash (rx) : ORIGIN = 0x9d000000, LENGTH = 512K
ram (rw!x): ORIGIN = 0x80000000, LENGTH = 26K
u0area (rw!x): ORIGIN = 0x80006800, LENGTH = 3K
uarea (rw!x): ORIGIN = 0x80007400, LENGTH = 3K
flash (rx) : ORIGIN = 0x9d005000, LENGTH = 492K
ram (rw!x): ORIGIN = 0x80000000, LENGTH = 0x62C0
u0area (rw!x): ORIGIN = 0x800062C0, LENGTH = 3K
uarea (rw!x): ORIGIN = 0x80006EC0, LENGTH = 3K
keram (rwx) : ORIGIN = 0x80007AC0, LENGTH = 0x540
/* Required by Microchip C32 linker */
kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x80000
kseg0_boot_mem : ORIGIN = 0x9FC00000, LENGTH = 0x1000
exception_mem : ORIGIN = 0x9FC00000, LENGTH = 0x1000
kseg1_boot_mem : ORIGIN = 0xBFC00000, LENGTH = 0
kseg0_boot_mem : ORIGIN = 0x9FC00490, LENGTH = 0x970
exception_mem : ORIGIN = 0x9FC01000, LENGTH = 0x1000
kseg1_boot_mem : ORIGIN = 0xBFC00000, LENGTH = 0x490
kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000
}
@@ -25,14 +26,18 @@ u0 = ORIGIN(u0area);
u = ORIGIN(uarea);
u_end = ORIGIN(uarea) + LENGTH(uarea);
_keram_start = ORIGIN(keram);
_keram_end = ORIGIN(keram) + LENGTH(keram);
SECTIONS
{
.text ORIGIN(flash) :
{
/* Exception handlers. */
*(.exception)
. = 0x1000;
/* Execution starts here. */
*(.startup)
*(.startup)
*(.text .stub .text.* .gnu.linkonce.t.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
@@ -63,7 +68,7 @@ SECTIONS
{
__bss_start = .;
*(.dynbss)
*(.sbss)
*(.sbss .sbss.*)
*(.scommon)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
@@ -75,6 +80,21 @@ SECTIONS
__bss_end = . ;
_end = .;
/*
* RAM functions go at the end of our stack and heap allocation.
* Alignment of 2K required by the boundary register (BMXDKPBA).
*/
.ramfunc : AT (LOADADDR (.data) + SIZEOF (.data))
{
_ramfunc_begin = . ;
*(.ramfunc .ramfunc.*)
. = ALIGN(4) ;
_ramfunc_end = . ;
} >keram
_ramfunc_image_begin = LOADADDR(.ramfunc) ;
_ramfunc_length = SIZEOF(.ramfunc) ;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }

13
sys/pic32/fubarino-uart-sramc/using-bootloader.ld → sys/pic32/32mxsdram-uart/using-bootloader.ld
View File

@@ -1,5 +1,5 @@
/*
* Linker script for PIC32 firmware using RetroBSD bootloader.
* Linker script for PIC32 firmware using HID bootloader.
*/
OUTPUT_FORMAT("elf32-littlemips", "elf32-bigmips",
"elf32-littlemips")
@@ -7,16 +7,16 @@ OUTPUT_ARCH(mips)
ENTRY(_reset_vector_)
MEMORY
{
flash (rx) : ORIGIN = 0x9d000000, LENGTH = 512K
flash (rx) : ORIGIN = 0x9d005000, LENGTH = 492K
ram (rw!x): ORIGIN = 0x80000000, LENGTH = 26K
u0area (rw!x): ORIGIN = 0x80006800, LENGTH = 3K
uarea (rw!x): ORIGIN = 0x80007400, LENGTH = 3K
/* Required by Microchip C32 linker */
kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x80000
kseg0_boot_mem : ORIGIN = 0x9FC00000, LENGTH = 0x1000
exception_mem : ORIGIN = 0x9FC00000, LENGTH = 0x1000
kseg1_boot_mem : ORIGIN = 0xBFC00000, LENGTH = 0
kseg0_boot_mem : ORIGIN = 0x9FC00490, LENGTH = 0x970
exception_mem : ORIGIN = 0x9FC01000, LENGTH = 0x1000
kseg1_boot_mem : ORIGIN = 0xBFC00000, LENGTH = 0x490
kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000
}
@@ -31,8 +31,9 @@ SECTIONS
{
/* Exception handlers. */
*(.exception)
. = 0x1000;
/* Execution starts here. */
*(.startup)
*(.startup)
*(.text .stub .text.* .gnu.linkonce.t.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)

3
sys/pic32/Makefile
View File

@@ -5,7 +5,8 @@ SUBDIR = baremetal dip duinomite duinomite-uart duinomite-e \
duinomite-e-uart explorer16 max32 max32-eth maximite \
meb pinguino-micro starter-kit ubw32 ubw32-uart \
ubw32-uart-sdram baremetal fubarino fubarino-uart \
fubarino-uart-sramc mmb-mx7 maximite-color
fubarino-uart-sramc mmb-mx7 maximite-color \
32mxsdram-uart
default:

17
sys/pic32/fubarino-uart-sramc/FUBARINO-UART-SRAMC
View File

@@ -1,17 +0,0 @@
# Fubarino SD with UART 2 enabled, USB console and SRAMC
core pic32mx7
mapping fubarino
linker bootloader
option PARTITION=sramc0:sa@1500,fs@2572
device kernel cpu_khz=80000 bus_khz=80000 invled=6
device console device=tty1
device uart2 baud=115200
device sd0 port=2 cs=SS
device adc
device glcd
device oc
device gpio
device sramc data=16 lda=5 rd=15 wr=14

76
sys/pic32/fubarino-uart-sramc/Makefile
View File

@@ -1,76 +0,0 @@
BUILDPATH = ../../../tools/configsys/../../sys/pic32
H = ../../../tools/configsys/../../sys/include
M = ../../../tools/configsys/../../sys/pic32
S = ../../../tools/configsys/../../sys/kernel
vpath %.c $(M):$(S)
vpath %.S $(M):$(S)
KERNOBJ += _startup.o adc.o clock.o cons.o devcfg.o devsw.o exception.o glcd.o gpio.o init_main.o init_sysent.o kern_clock.o kern_descrip.o kern_exec.o kern_exit.o kern_fork.o kern_mman.o kern_proc.o kern_prot.o kern_prot2.o kern_resource.o kern_sig.o kern_sig2.o kern_subr.o kern_synch.o kern_sysctl.o kern_time.o machdep.o mem.o oc.o rd_sd.o rd_sramc.o rdisk.o signal.o spi_bus.o subr_prf.o subr_rmap.o swap.o sys_generic.o sys_inode.o sys_pipe.o sys_process.o syscalls.o sysctl.o tty.o tty_subr.o tty_tty.o uart.o ufs_alloc.o ufs_bio.o ufs_bmap.o ufs_dsort.o ufs_fio.o ufs_inode.o ufs_mount.o ufs_namei.o ufs_subr.o ufs_syscalls.o ufs_syscalls2.o vers.o vfs_vnops.o vm_sched.o vm_swap.o vm_swp.o
EXTRA_TARGETS =
DEFS += -DADC_ENABLED=YES
DEFS += -DBUS_DIV=1
DEFS += -DBUS_KHZ=80000
DEFS += -DCONSOLE_DEVICE=tty1
DEFS += -DCPU_IDIV=2
DEFS += -DCPU_KHZ=80000
DEFS += -DCPU_MUL=20
DEFS += -DCPU_ODIV=1
DEFS += -DCRYSTAL=8
DEFS += -DDC0_DEBUG=DEVCFG0_DEBUG_DISABLED
DEFS += -DDC0_ICE=0
DEFS += -DDC1_CKM=0
DEFS += -DDC1_CKS=0
DEFS += -DDC1_FNOSC=DEVCFG1_FNOSC_PRIPLL
DEFS += -DDC1_IESO=DEVCFG1_IESO
DEFS += -DDC1_OSCIOFNC=0
DEFS += -DDC1_PBDIV=DEVCFG1_FPBDIV_1
DEFS += -DDC1_POSCMOD=DEVCFG1_POSCMOD_HS
DEFS += -DDC1_SOSC=0
DEFS += -DDC1_WDTEN=0
DEFS += -DDC1_WDTPS=DEVCFG1_WDTPS_1
DEFS += -DDC2_PLLIDIV=DEVCFG2_FPLLIDIV_2
DEFS += -DDC2_PLLMUL=DEVCFG2_FPLLMUL_20
DEFS += -DDC2_PLLODIV=DEVCFG2_FPLLODIV_1
DEFS += -DDC2_UPLL=0
DEFS += -DDC2_UPLLIDIV=DEVCFG2_UPLLIDIV_2
DEFS += -DDC3_CAN=DEVCFG3_FCANIO
DEFS += -DDC3_ETH=DEVCFG3_FETHIO
DEFS += -DDC3_MII=DEVCFG3_FMIIEN
DEFS += -DDC3_SRS=DEVCFG3_FSRSSEL_7
DEFS += -DDC3_USBID=DEVCFG3_FUSBIDIO
DEFS += -DDC3_USERID=0xffff
DEFS += -DDC3_VBUSON=DEVCFG3_FVBUSONIO
DEFS += -DGLCD_ENABLED=YES
DEFS += -DGPIO_ENABLED=YES
DEFS += -DKERNEL
DEFS += -DLED_KERNEL_INVERT=YES
DEFS += -DLED_KERNEL_PIN=14
DEFS += -DLED_KERNEL_PORT=TRISC
DEFS += -DOC_ENABLED=YES
DEFS += -DPARTITION="sramc0:sa@1500,fs@2572"
DEFS += -DPIC32MX7
DEFS += -DSD0_CS_PIN=9
DEFS += -DSD0_CS_PORT=TRISG
DEFS += -DSD0_PORT=2
DEFS += -DSRAMC_ENABLED=YES
DEFS += -DSW_DATA_PIN=0
DEFS += -DSW_DATA_PORT=TRISE
DEFS += -DSW_LDA_PIN=13
DEFS += -DSW_LDA_PORT=TRISC
DEFS += -DSW_RD_PIN=1
DEFS += -DSW_RD_PORT=TRISF
DEFS += -DSW_WR_PIN=0
DEFS += -DSW_WR_PORT=TRISF
DEFS += -DUART2_BAUD=115200
DEFS += -DUART2_ENABLED=YES
DEFS += -DUCB_METER
LDSCRIPT = ../../../tools/configsys/../../sys/pic32/cfg/bootloader.ld
CONFIG = FUBARINO-UART-SRAMC
CONFIGPATH = ../../../tools/configsys
include ../../../tools/configsys/../../sys/pic32/kernel-post.mk

50
sys/pic32/fubarino-uart-sramc/Makefile.local
View File

@@ -1,50 +0,0 @@
# CPU frequency 80 MHz.
DEFS += -DCPU_KHZ=80000
DEFS += -DBUS_KHZ=80000
DEFS += -DSRAMC_ENABLED
DEFS += -DPARTITION="sramc0:sa@1500,fs@2572"
#DEFS += -DROOT='makedev(0,1)'
#DEFS += -DSWAP='makedev(0,2)'
#
# Fubarino SD board
# =================
#
# Console on UART2
DEFS += -DCONSOLE_UART2 -DCONSOLE_BAUD=115200
# SD/MMC card driver on SPI2
# /CS0 at pin G9
DEFS += -DSD0_PORT=2
DEFS += -DSD0_CS_PORT=TRISG -DSD0_CS_PIN=9
# LED at pin C14
DEFS += -DLED_KERNEL_PORT=TRISC -DLED_KERNEL_PIN=14 -DLED_KERNEL_INVERT
# Swap on external device, 2 Mbytes
# data at E0-E7
# rd at F1
# wr at F0
# ldaddr at C13
DEFS += -DSWAPDEV=0x0100 -DSWAPSZ=2048
DEFS += -DSW_DATA_PORT=TRISE -DSW_DATA_PIN=0
DEFS += -DSW_RD_PORT=TRISF -DSW_RD_PIN=1
DEFS += -DSW_WR_PORT=TRISF -DSW_WR_PIN=0
DEFS += -DSW_LDA_PORT=TRISC -DSW_LDA_PIN=13
# Include or exclude drivers
DRIVER_GPIO = yes
# General Purpose I/O
DRIVER_ADC = yes
# Basic ADC interface
DRIVER_SPI = yes
# Generic SPI interface
DRIVER_OC = yes
# Output Compare driver

144
sys/pic32/fubarino-uart-sramc/Makefile_old
View File

@@ -1,144 +0,0 @@
H = ../../include
M = ..
S = ../../kernel
vpath %.c $(M):$(S)
vpath %.S $(M):$(S)
# Kernel options.
DEFS += -I. -I$(H) -DKERNEL -DUCB_METER -DPIC32MX7
# CPU frequency 80 MHz.
DEFS += -DCPU_KHZ=80000
DEFS += -DBUS_KHZ=80000
DEFS += -DSRAMC_ENABLED
DEFS += -DPARTITION="sramc0:sa@1500,fs@2572"
#DEFS += -DROOT='makedev(0,1)'
#DEFS += -DSWAP='makedev(0,2)'
#
# Fubarino SD board
# =================
#
# Console on UART2
DEFS += -DCONSOLE_UART2 -DCONSOLE_BAUD=115200
# SD/MMC card driver on SPI2
# /CS0 at pin G9
DEFS += -DSD0_PORT=2
DEFS += -DSD0_CS_PORT=TRISG -DSD0_CS_PIN=9
# LED at pin E5
DEFS += -DLED_KERNEL_PORT=TRISC -DLED_KERNEL_PIN=14 -DLED_KERNEL_INVERT
# Swap on external device, 2 Mbytes
# data at E0-E7
# rd at F0
# wr at F1
# ldaddr at G9
DEFS += -DSWAPDEV=0x0100 -DSWAPSZ=2048
DEFS += -DSW_DATA_PORT=TRISE -DSW_DATA_PIN=0
DEFS += -DSW_RD_PORT=TRISF -DSW_RD_PIN=1
DEFS += -DSW_WR_PORT=TRISF -DSW_WR_PIN=0
DEFS += -DSW_LDA_PORT=TRISC -DSW_LDA_PIN=13
# Include or exclude drivers
DRIVER_GPIO = yes
# General Purpose I/O
DRIVER_ADC = yes
# Basic ADC interface
DRIVER_SPI = yes
# Generic SPI interface
DRIVER_OC = yes
# Output Compare driver
DEPFLAGS = -MT $@ -MD -MP -MF .deps/$*.dep
CFLAGS = -O $(DEFS) $(DEPFLAGS)
ASFLAGS = $(DEFS) $(DEPFLAGS)
include ../gcc-config.mk
CC = $(GCCPREFIX)gcc -EL -g -mips32r2
CC += -nostdinc -fno-builtin -Werror -Wall -fno-dwarf2-cfi-asm
LDFLAGS += -nostdlib -T using-bootloader.ld -Wl,-Map=unix.map
SIZE = $(GCCPREFIX)size
OBJDUMP = $(GCCPREFIX)objdump
OBJCOPY = $(GCCPREFIX)objcopy
PROGTOOL = $(AVRDUDE) -c stk500v2 -p pic32 -b 115200
# Machine-dependent files:
# startup.o MUST be loaded first.
KERNOBJ = startup.o clock.o devsw.o sysctl.o \
signal.o machdep.o mem.o exception.o
KERNOBJ += cons.o rd_sramc.o
# Kernel.
KERNOBJ += init_main.o init_sysent.o kern_clock.o \
kern_descrip.o kern_exec.o kern_exit.o kern_fork.o \
kern_mman.o kern_proc.o kern_prot.o \
kern_prot2.o kern_resource.o kern_sig.o kern_sig2.o \
kern_subr.o kern_synch.o kern_sysctl.o kern_time.o \
subr_log.o subr_prf.o subr_rmap.o \
sys_generic.o sys_inode.o syscalls.o \
sys_pipe.o sys_process.o tty.o tty_conf.o \
tty_subr.o tty_tty.o ufs_alloc.o ufs_bio.o \
ufs_bmap.o ufs_dsort.o ufs_fio.o \
ufs_inode.o ufs_mount.o ufs_namei.o ufs_subr.o \
ufs_syscalls.o ufs_syscalls2.o vfs_vnops.o \
vm_sched.o vm_swap.o vm_swp.o kern_glob.o swap.o spi_bus.o
# Drivers.
KERNOBJ += rdisk.o rd_sd.o
# Configuration-dependent files.
KERNOBJ += vers.o
# Include any local specific configuration overrides
-include Makefile.local
# This makefile does the work including the right files and options for the drivers
include ../drivers.mk
all: .deps sys machine unix.elf
$(SIZE) unix.elf
clean:
rm -rf .deps *.o *.elf *.bin *.dis *.map *.srec core \
mklog assym.h vers.c genassym sys machine
.deps:
mkdir .deps
sys:
ln -s ../../include $@
machine:
ln -s .. $@
unix.elf: $(KERNOBJ) using-bootloader.ld
$(CC) $(LDFLAGS) $(KERNOBJ) -o $@
chmod -x $@
$(OBJDUMP) -d -S $@ > unix.dis
$(OBJCOPY) -O binary $@ unix.bin
$(OBJCOPY) -O ihex --change-addresses=0x80000000 $@ unix.hex
chmod -x $@ unix.bin
load: unix.hex
pic32prog unix.hex
vers.o: ../newvers.sh $(H)/*.h $(M)/*.[ch] $(S)/*.c
sh ../newvers.sh > vers.c
$(CC) -c vers.c
.SUFFIXES: .i .srec .hex .dis .cpp .cxx .bin .elf
.o.dis:
$(OBJDUMP) -d -z -S $< > $@
ifeq (.deps, $(wildcard .deps))
-include .deps/*.dep
endif

14
sys/pic32/fubarino-uart/FUBARINO-UART
View File

@@ -1,14 +0,0 @@
# Fubarino configuration file
core pic32mx7
mapping fubarino
linker bootloader
device kernel led=21 cpu_khz=80000 bus_khz=80000
device console device=tty1
device uart2 baud=115200
device sd0 port=2 cs=SS
device adc
device glcd
device oc
device gpio

65
sys/pic32/fubarino-uart/Makefile
View File

@@ -1,65 +0,0 @@
BUILDPATH = ../../../tools/configsys/../../sys/pic32
H = ../../../tools/configsys/../../sys/include
M = ../../../tools/configsys/../../sys/pic32
S = ../../../tools/configsys/../../sys/kernel
vpath %.c $(M):$(S)
vpath %.S $(M):$(S)
KERNOBJ += _startup.o adc.o clock.o cons.o devcfg.o devsw.o exception.o glcd.o gpio.o init_main.o init_sysent.o kern_clock.o kern_descrip.o kern_exec.o kern_exit.o kern_fork.o kern_mman.o kern_proc.o kern_prot.o kern_prot2.o kern_resource.o kern_sig.o kern_sig2.o kern_subr.o kern_synch.o kern_sysctl.o kern_time.o machdep.o mem.o oc.o rd_sd.o rdisk.o signal.o spi_bus.o subr_prf.o subr_rmap.o swap.o sys_generic.o sys_inode.o sys_pipe.o sys_process.o syscalls.o sysctl.o tty.o tty_subr.o tty_tty.o uart.o ufs_alloc.o ufs_bio.o ufs_bmap.o ufs_dsort.o ufs_fio.o ufs_inode.o ufs_mount.o ufs_namei.o ufs_subr.o ufs_syscalls.o ufs_syscalls2.o vers.o vfs_vnops.o vm_sched.o vm_swap.o vm_swp.o
EXTRA_TARGETS =
DEFS += -DADC_ENABLED=YES
DEFS += -DBUS_DIV=1
DEFS += -DBUS_KHZ=80000
DEFS += -DCONSOLE_DEVICE=tty1
DEFS += -DCPU_IDIV=2
DEFS += -DCPU_KHZ=80000
DEFS += -DCPU_MUL=20
DEFS += -DCPU_ODIV=1
DEFS += -DCRYSTAL=8
DEFS += -DDC0_DEBUG=DEVCFG0_DEBUG_DISABLED
DEFS += -DDC0_ICE=0
DEFS += -DDC1_CKM=0
DEFS += -DDC1_CKS=0
DEFS += -DDC1_FNOSC=DEVCFG1_FNOSC_PRIPLL
DEFS += -DDC1_IESO=DEVCFG1_IESO
DEFS += -DDC1_OSCIOFNC=0
DEFS += -DDC1_PBDIV=DEVCFG1_FPBDIV_1
DEFS += -DDC1_POSCMOD=DEVCFG1_POSCMOD_HS
DEFS += -DDC1_SOSC=0
DEFS += -DDC1_WDTEN=0
DEFS += -DDC1_WDTPS=DEVCFG1_WDTPS_1
DEFS += -DDC2_PLLIDIV=DEVCFG2_FPLLIDIV_2
DEFS += -DDC2_PLLMUL=DEVCFG2_FPLLMUL_20
DEFS += -DDC2_PLLODIV=DEVCFG2_FPLLODIV_1
DEFS += -DDC2_UPLL=0
DEFS += -DDC2_UPLLIDIV=DEVCFG2_UPLLIDIV_2
DEFS += -DDC3_CAN=DEVCFG3_FCANIO
DEFS += -DDC3_ETH=DEVCFG3_FETHIO
DEFS += -DDC3_MII=DEVCFG3_FMIIEN
DEFS += -DDC3_SRS=DEVCFG3_FSRSSEL_7
DEFS += -DDC3_USBID=DEVCFG3_FUSBIDIO
DEFS += -DDC3_USERID=0xffff
DEFS += -DDC3_VBUSON=DEVCFG3_FVBUSONIO
DEFS += -DGLCD_ENABLED=YES
DEFS += -DGPIO_ENABLED=YES
DEFS += -DKERNEL
DEFS += -DLED_KERNEL_PIN=5
DEFS += -DLED_KERNEL_PORT=TRISE
DEFS += -DOC_ENABLED=YES
DEFS += -DPIC32MX7
DEFS += -DSD0_CS_PIN=9
DEFS += -DSD0_CS_PORT=TRISG
DEFS += -DSD0_PORT=2
DEFS += -DUART2_BAUD=115200
DEFS += -DUART2_ENABLED=YES
DEFS += -DUCB_METER
LDSCRIPT = ../../../tools/configsys/../../sys/pic32/cfg/bootloader.ld
CONFIG = FUBARINO-UART
CONFIGPATH = ../../../tools/configsys
include ../../../tools/configsys/../../sys/pic32/kernel-post.mk

73
sys/pic32/fubarino/FUBARINO-UART2CONS-UART1-SRAMC Normal file
View File

@@ -0,0 +1,73 @@
# Fubarino SD with UART2 console, UART1 enabled and with SRAMC SWAPDISK
#
core pic32mx7
# ! pin numbers here are the pin Ns. printed out on Fubarino board (ie. 12, 23)
mapping fubarino
linker bootloader
# 4MB CPLD sram ramdisk, BB, swap and filesystem, ! nmount=3 (rootfs+swap+tmpfs)
#option PARTITION=sramc0:sa@1500,fs@2572
#option PARTITION=sramc0:sa@1024,fs@3000
#device sramc data=16 lda=5 rd=15 wr=14
# 8MB CPLD sram ramdisk, PMP bus, swap and filesystem, ! nmount=3 (rootfs+swap+tmpfs)
# change the sramc-size in rd_sramc.c as well
option PARTITION=sramc0:sa@2048,fs@6140
# no pins defs - using PMP bus
device sramc
option nmount=3
device kernel cpu_khz=120000 bus_khz=120000 led=21
# Console UART2, tty = UART - 1
device console device=tty1
device uart2 baud=115200
# Additional UART1
device uart1 baud=115200
# SDcard
device sd0 port=2 cs=SS mhz=20
# NPROC=25 MAX
option nproc=25
option hz=1000
option nbuf=8
device adc
device spi
device oc
device gpio
# Bootloader section:
device bootloader led=21 button=23 crystal=8 jump=0x9d000000
# clock = crystal / pllidiv * pllmul
# usb == 48MHz = crystal / upllidiv * 12
# Bootloader: for 40MHz clock:
# option crystal=8
# option pllidiv=3
# option pllmul=15
# option upllidiv=2
# Bootloader: for 80MHz clock:
# option crystal=8
# option pllidiv=2
# option pllmul=20
# option upllidiv=2
# Bootloader: for 96MHz clock:
# option crystal=8
# option pllidiv=2
# option pllmul=24
# option upllidiv=2
# Bootloader: for 120MHz clock:
option crystal=8
option pllidiv=1
option pllmul=15
option upllidiv=2

289
sys/pic32/rd_sramc.c
View File

@@ -1,20 +1,22 @@
/*
* Driver for external RAM-based swap device.
* Driver for external SRAM-CPLD based Swap and Filesystem devices
*
* This version is for 8MB RAMDISK v.1.1 and compatible
* Pito 7.4.2014 - PIC32MX PMP bus version
* Under by retrobsd.org used Licence
* No warranties of any kind
*
* Interface:
* data[7:0] - connected to PORTx
* rd - fetch a byte from memory to data[7:0], increment address
* wr - write a byte data[7:0] to memory, increment address
* ldaddr - write address from data[7:0] in 3 steps: low-middle-high
* PMD<7:0> - connected to PMP data bus
* PMRD - fetch a byte from memory to data<7:0>, increment address, PMRD
* PMWR - write a byte data[7:0] to memory, increment address, PMWR
* PMA0 - HIGH - write Address from data<3:0> in 6 steps: high nibble ... low nibble
* - LOW - write/read Data
*
* Signals PMRD, PMWR are active LOW and idle HIGH
* Signal PMA0 is LOW when accessing RAM Data, and HIGH when accessing RAM Addresses
*
*
* Signals rd, wr, ldadr are active LOW and idle HIGH.
* To activate, you need to pulse it high-low-high.
* CHANGE: IM 23.12.2011 - signals active LOW
* CHANGE: IM 24.12.2011 - finetuning for 55ns SRAM and 7ns CPLD
* - some nops removed
* - nops marked 55ns are required !!!
* - MAX performance settings for 55ns SRAM
* CHANGE: IM 28.12.2011 - dev_load_address is 6x4bit now
*/
#include "param.h"
#include "systm.h"
@@ -27,130 +29,86 @@
int sw_dkn = -1; /* Statistics slot number */
/*
* Set data output value.
*/
static inline void data_set (unsigned char byte)
{
LAT_CLR(SW_DATA_PORT) = 0xff << SW_DATA_PIN;
LAT_SET(SW_DATA_PORT) = byte << SW_DATA_PIN;
}
// Ramdisk v.1.1. wiring
// PMP RAMDISK
// ===================
// PMD<D0-D7> D0-D7
// PMRD /RD
// PMWR /WR
// PMA<0> /DATA
// RD and WR pulses duration settings
// Minimal recommended settings, increase them when unstable
// No warranties of any kind
// for 120MHz clock, 70ns PSRAM, Ramdisk v.1.1.
#define ADR_PULSE 1
#define WR_PULSE 5
#define RD_PULSE 11
// for 80MHz clock, 70ns PSRAM, Ramdisk v.1.1.
//#define ADR_PULSE 1
//#define WR_PULSE 3
//#define RD_PULSE 8
// for 120MHz clock, 55ns SRAM
//#define ADR_PULSE 1
//#define WR_PULSE 3
//#define RD_PULSE 6
// for 80MHz clock, 55ns SRAM
//#define ADR_PULSE 1
//#define WR_PULSE 2
//#define RD_PULSE 4
typedef union {
unsigned value;
struct {
unsigned nib1: 4; // lowest nibble
unsigned nib2: 4;
unsigned nib3: 4;
unsigned nib4: 4;
unsigned nib5: 4;
unsigned nib6: 4;
unsigned nib7: 4;
unsigned nib8: 4; // highest nibble
};
} nybbles ;
/*
* Switch data bus to input.
* Load the 24 bit address to Ramdisk.
*
*/
static inline void data_switch_input ()
{
LAT_CLR(SW_DATA_PORT) = 0xff << SW_DATA_PIN; // !!! PIC32 errata
TRIS_SET(SW_DATA_PORT) = 0xff << SW_DATA_PIN;
asm volatile ("nop");
}
/*
* Switch data bus to output.
*/
static inline void data_switch_output ()
{
TRIS_CLR(SW_DATA_PORT) = 0xff << SW_DATA_PIN;
asm volatile ("nop");
}
/*
* Get data input value.
*/
static inline unsigned char data_get ()
{
return PORT_VAL(SW_DATA_PORT) >> SW_DATA_PIN;
}
/*
* Send LDA pulse: high-low-high.
*/
static inline void lda_pulse ()
{
LAT_CLR(SW_LDA_PORT) = 1 << SW_LDA_PIN;
asm volatile ("nop");
asm volatile ("nop");
LAT_SET(SW_LDA_PORT) = 1 << SW_LDA_PIN;
}
/*
* Set RD low.
* Minimal time between falling edge of RD to data valid is 50ns.
*/
static inline void rd_low ()
{
LAT_CLR(SW_RD_PORT) = 1 << SW_RD_PIN;
#if BUS_KHZ > 33000
asm volatile ("nop"); // 55ns
asm volatile ("nop"); // 55ns
#endif
#if BUS_KHZ > 66000
asm volatile ("nop"); // 55ns
asm volatile ("nop"); // 55ns
#endif
}
/*
* Set RD high.
*/
static inline void rd_high ()
{
LAT_SET(SW_RD_PORT) = 1 << SW_RD_PIN;
}
/*
* Send WR pulse: high-low-high.
* It shall be minimally 40ns.
*/
static inline void wr_pulse ()
{
LAT_CLR(SW_WR_PORT) = 1 << SW_WR_PIN;
#if BUS_KHZ > 33000
asm volatile ("nop"); // 55ns
asm volatile ("nop"); // 55ns
#endif
#if BUS_KHZ > 66000
asm volatile ("nop"); // 55ns
#endif
LAT_SET(SW_WR_PORT) = 1 << SW_WR_PIN;
}
/*
* Load the 24 bit address to ramdisk.
* Leave data bus in input mode.
*/
static void
inline static void
dev_load_address (addr)
unsigned addr;
{
/* Toggle rd: make one dummy read - this clears cpld's addr pointer */
rd_low ();
rd_high ();
nybbles temp;
temp.value = addr;
data_switch_output(); /* switch data bus to output */
while(PMMODE & 0x8000); // Poll - if busy, wait
data_set (addr); /* send lowest 4 bits */
lda_pulse(); /* pulse ldaddr */
PMADDR = 1; // set ADR mode (1) to write the Address
data_set (addr >> 4); /* send 4 bits */
lda_pulse(); /* pulse ldaddr */
PMMODE = 0b10<<8 | (ADR_PULSE<<2); // full ADR speed
data_set (addr >> 8); /* send 4 bits */
lda_pulse(); /* pulse ldaddr */
PMDIN = temp.nib6; /* write 4 bits */
while(PMMODE & 0x8000); // Poll - if busy, wait
PMDIN = temp.nib5; /* write 4 bits */
while(PMMODE & 0x8000); // Poll - if busy, wait
PMDIN = temp.nib4; /* write 4 bits */
while(PMMODE & 0x8000); // Poll - if busy, wait
PMDIN = temp.nib3; /* write 4 bits */
data_set (addr >> 12); /* send 4 bits */
lda_pulse(); /* pulse ldaddr */
while(PMMODE & 0x8000); // Poll - if busy, wait
PMDIN = temp.nib2; /* write 4 bits */
data_set (addr >> 16); /* send 4 bits */
lda_pulse(); /* pulse ldaddr */
while(PMMODE & 0x8000); // Poll - if busy, wait
PMDIN = temp.nib1; /* write 4 bits */
data_set (addr >> 20); /* send highest 4 bits */
lda_pulse(); /* pulse ldaddr */
data_switch_input();
}
/*
@@ -159,13 +117,13 @@ dev_load_address (addr)
*/
int sramc_size ( int unit )
{
return 4096;
return 8192; // 4096 for 4MB ramdisk
}
/*
* Read a block of data.
*/
int sramc_read (int unit, unsigned int blockno, char *data, unsigned int nbytes)
inline int sramc_read (int unit, unsigned int blockno, char *data, unsigned int nbytes)
{
int i;
@@ -174,42 +132,49 @@ int sramc_read (int unit, unsigned int blockno, char *data, unsigned int nbytes)
dev_load_address (blockno * DEV_BSIZE);
data_switch_input(); /* switch data bus to input */
/* Read data. */
/* Read data. */
while(PMMODE & 0x8000); // Poll - if busy, wait
PMADDR = 0; // set DATA mode (0)
PMMODE = 0b10<<8 | (RD_PULSE<<2); // read slowly
PMDIN; // Read the PMDIN to clear previous data and latch new data
for (i=0; i<nbytes; i++) {
rd_low(); /* set rd LOW */
*data++ = data_get(); /* read a byte of data */
rd_high(); /* set rd HIGH */
while(PMMODE & 0x8000); // Poll - if busy, wait before reading
*data++ = PMDIN; /* read a byte of data */
}
return 1;
}
/*
* Write a block of data.
*/
int sramc_write (int unit, unsigned int blockno, char *data, unsigned int nbytes)
inline int sramc_write (int unit, unsigned int blockno, char *data, unsigned int nbytes)
{
unsigned i;
//DEBUG9("sramc%d: write block %u, length %u bytes, addr %p\n",
// major(dev), blockno, nbytes, data);
dev_load_address (blockno * DEV_BSIZE);
dev_load_address (blockno * DEV_BSIZE);
data_switch_output(); /* switch data bus to output */
/* Write data. */
while (PMMODE & 0x8000); // Poll - if busy, wait
PMADDR = 0; // set DATA mode (0)
PMMODE = 0b10<<8 | (WR_PULSE<<2); // faster with write
for (i=0; i<nbytes; i++) {
data_set (*data); /* send a byte of data */
data++;
wr_pulse(); /* pulse wr */
while(PMMODE & 0x8000); // Poll - if busy, wait
PMDIN = (*data++); /* write a byte of data */
}
/* Switch data bus to input. */
data_switch_input();
return 1;
}
@@ -220,23 +185,33 @@ int sramc_write (int unit, unsigned int blockno, char *data, unsigned int nbytes
void sramc_init (int unit)
{
struct buf *bp;
if (TRIS_VAL(SW_LDA_PORT) & (1 << SW_LDA_PIN)) {
/* Initialize hardware.
* Switch data bus to input. */
data_switch_input();
// Initialize PMP hardware
PMCON = 0; // disable PMP
asm volatile ("nop"); // Errata
PMCON = 1<<9 | 1<<8; // Enable RD and WR
// MODE WAITB WAITM WAITE
PMMODE = 0b10<<8 | 0 | (14<<2) | 0 ; // Mode2 Master 8bit
PMAEN = 1; // PMA<0>, use A0 only
PMADDR = 0; // start with DATA mode
PMCONSET = 1<<15; // PMP enabled
asm volatile ("nop");
// make a couple of dummy reads - it refreshes the cpld internals a little bit :)
while(PMMODE & 0x8000); // Poll - if busy, wait before reading
PMDIN; /* read a byte of data */
while(PMMODE & 0x8000); // Poll - if busy, wait before reading
PMDIN; /* read a byte of data */
PMADDR = 1; // go with with ADDRESS mode now
/* Set idle HIGH rd, wr and ldaddr as output pins. */
LAT_SET(SW_RD_PORT) = 1 << SW_RD_PIN;
LAT_SET(SW_WR_PORT) = 1 << SW_WR_PIN;
LAT_SET(SW_LDA_PORT) = 1 << SW_LDA_PIN;
TRIS_CLR(SW_RD_PORT) = 1 << SW_RD_PIN;
TRIS_CLR(SW_WR_PORT) = 1 << SW_WR_PIN;
TRIS_CLR(SW_LDA_PORT) = 1 << SW_LDA_PIN;
/* Toggle rd: make one dummy read. */
rd_low(); /* set rd low */
rd_high(); /* set rd high */
}
DEBUG3("sramc%d: init done\n",unit);
bp = prepartition_device("sramc0");
if(bp)