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Merged Iain Buclaw's AMD 3dNow! asm changes.

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This commit is contained in:
Robert Clipsham
2010-12-09 22:27:14 +00:00
parent 4b97c6b6a2
commit 496a87e452
2 changed files with 44 additions and 0 deletions
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23
gen/asm-x86-32.h
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@@ -948,6 +948,7 @@ namespace AsmParserx8632
{ "pand", Op_DstSrcMMX },
{ "pandn", Op_DstSrcMMX },
{ "pavgb", Op_DstSrcMMX },
{ "pavgusb", Op_DstSrcMMX }, // AMD 3dNow!
{ "pavgw", Op_DstSrcMMX },
{ "pcmpeqb", Op_DstSrcMMX },
{ "pcmpeqd", Op_DstSrcMMX },
@@ -956,6 +957,25 @@ namespace AsmParserx8632
{ "pcmpgtd", Op_DstSrcMMX },
{ "pcmpgtw", Op_DstSrcMMX },
{ "pextrw", Op_DstSrcImmM }, // gpr32 dest
{ "pf2id", Op_DstSrcMMX }, // %% AMD 3dNow! opcodes
{ "pfacc", Op_DstSrcMMX },
{ "pfadd", Op_DstSrcMMX },
{ "pfcmpeq", Op_DstSrcMMX },
{ "pfcmpge", Op_DstSrcMMX },
{ "pfcmpgt", Op_DstSrcMMX },
{ "pfmax", Op_DstSrcMMX },
{ "pfmin", Op_DstSrcMMX },
{ "pfmul", Op_DstSrcMMX },
{ "pfnacc", Op_DstSrcMMX }, // 3dNow values are returned in MM0 register,
{ "pfpnacc", Op_DstSrcMMX }, // so should be correct to use Op_DstSrcMMX.
{ "pfrcp", Op_DstSrcMMX },
{ "pfrcpit1", Op_DstSrcMMX },
{ "pfrcpit2", Op_DstSrcMMX },
{ "pfrsqit1", Op_DstSrcMMX },
{ "pfrsqrt", Op_DstSrcMMX },
{ "pfsub", Op_DstSrcMMX },
{ "pfsubr", Op_DstSrcMMX },
{ "pi2fd", Op_DstSrcMMX }, // %%
{ "pinsrw", Op_DstSrcImmM }, // gpr32(16), mem16 src, sse too
{ "pmaddwd", Op_DstSrcMMX },
{ "pmaxsw", Op_DstSrcMMX },
@@ -963,6 +983,8 @@ namespace AsmParserx8632
{ "pminsw", Op_DstSrcMMX },
{ "pminub", Op_DstSrcMMX },
{ "pmovmskb", Op_DstSrcMMX },
{ "pmulhrw", Op_DstSrcMMX }, // AMD 3dNow!
{ "pmulhuw", Op_DstSrcMMX },
{ "pmulhw", Op_DstSrcMMX },
{ "pmullw", Op_DstSrcMMX },
@@ -1000,6 +1022,7 @@ namespace AsmParserx8632
{ "psubusb", Op_DstSrcMMX },
{ "psubusw", Op_DstSrcMMX },
{ "psubw", Op_DstSrcMMX },
{ "pswapd", Op_DstSrcMMX }, // AMD 3dNow!
{ "punpckhbw", Op_DstSrcMMX },
{ "punpckhdq", Op_DstSrcMMX },
{ "punpckhqdq",Op_DstSrcMMX },

21
gen/asm-x86-64.h
View File

@@ -1058,6 +1058,7 @@ namespace AsmParserx8664
{ "pandn", Op_DstSrcMMX },
{ "pause", Op_DstSrcMMX },
{ "pavgb", Op_DstSrcMMX },
{ "pavgusb", Op_DstSrcMMX }, // AMD 3dNow!
{ "pavgw", Op_DstSrcMMX },
{ "pcmpeqb", Op_DstSrcMMX },
{ "pcmpeqd", Op_DstSrcMMX },
@@ -1066,6 +1067,25 @@ namespace AsmParserx8664
{ "pcmpgtd", Op_DstSrcMMX },
{ "pcmpgtw", Op_DstSrcMMX },
{ "pextrw", Op_DstSrcImmM }, // gpr32 dest
{ "pf2id", Op_DstSrcMMX }, // %% AMD 3dNow! opcodes
{ "pfacc", Op_DstSrcMMX },
{ "pfadd", Op_DstSrcMMX },
{ "pfcmpeq", Op_DstSrcMMX },
{ "pfcmpge", Op_DstSrcMMX },
{ "pfcmpgt", Op_DstSrcMMX },
{ "pfmax", Op_DstSrcMMX },
{ "pfmin", Op_DstSrcMMX },
{ "pfmul", Op_DstSrcMMX },
{ "pfnacc", Op_DstSrcMMX }, // 3dNow values are returned in MM0 register,
{ "pfpnacc", Op_DstSrcMMX }, // so should be correct to use Op_DstSrcMMX.
{ "pfrcp", Op_DstSrcMMX },
{ "pfrcpit1", Op_DstSrcMMX },
{ "pfrcpit2", Op_DstSrcMMX },
{ "pfrsqit1", Op_DstSrcMMX },
{ "pfrsqrt", Op_DstSrcMMX },
{ "pfsub", Op_DstSrcMMX },
{ "pfsubr", Op_DstSrcMMX },
{ "pi2fd", Op_DstSrcMMX }, // %%
{ "phaddd", Op_DstSrcSSE },
{ "phaddsw", Op_DstSrcSSE },
{ "phaddw", Op_DstSrcSSE },
@@ -1120,6 +1140,7 @@ namespace AsmParserx8664
{ "psubusb", Op_DstSrcMMX },
{ "psubusw", Op_DstSrcMMX },
{ "psubw", Op_DstSrcMMX },
{ "pswapd", Op_DstSrcMMX }, // AMD 3dNow!
{ "punpckhbw", Op_DstSrcMMX },
{ "punpckhdq", Op_DstSrcMMX },
{ "punpckhqdq",Op_DstSrcMMX },