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https://github.com/kelvinlawson/atomthreads.git
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This commit is contained in:
Natie van Rooyen
@@ -10,5 +10,6 @@ QEMU ARM Integrator/CP (ARM926EJ-S) Platform
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The "qemu_integratorcp" platform contains sources for building a sample
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Atomthreads application for the ARM Integrator/CP (ARM926EJ-S) platform.
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BUGS:
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kern4 testcase fails (sometimes).
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@@ -46,16 +46,16 @@ ICP_PIC_T * const board_pic = (ICP_PI
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void
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dbg_format_msg (char *format, ...)
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{
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va_list args;
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static char msg[256] ;
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va_list args;
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static char msg[256] ;
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CRITICAL_STORE ;
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va_start (args, format) ;
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CRITICAL_START() ;
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vsnprintf ((char*)msg, 256, (char*)format, args) ;
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vsnprintf ((char*)msg, 256, (char*)format, args) ;
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printf (msg) ;
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CRITICAL_END() ;
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printf (msg) ;
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}
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/**
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@@ -59,21 +59,21 @@ typedef struct ICP_TIMER_S {
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// -------- ICP_TIMER_LOAD : (LOAD Offset: 0x00) Load value for Timer --------
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// -------- ICP_TIMER_VALUE : (LOAD Offset: 0x04) The current value for Timer --------
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// -------- ICP_TIMER_CONTROL : (CONTROL Offset: 0x04) Timer control register --------
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#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask
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#define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled.
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#define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count..
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#define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable.
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#define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s.
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#define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor
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#define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) //
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#define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) //
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#define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) //
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#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0.
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#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode
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#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask
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#define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled.
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#define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count..
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#define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable.
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#define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s.
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#define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor
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#define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) //
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#define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) //
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#define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) //
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#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0.
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#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode
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// -------- ICP_TIMER_INTCLR : (INTCLR Offset: 0x0C) Timer interrupt clear --------
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// -------- ICP_TIMER_RIS : (RIS Offset: 0x10) Timer raw interrupt status --------
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// -------- ICP_TIMER_MIS : (MIS Offset: 0x14) Timer masked interrupt status --------
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#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt
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#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt
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// -------- ICP_TIMER_BGLOAD : (BGLOAD Offset: 0x18) Timer masked interrupt status --------
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@@ -100,19 +100,19 @@ typedef struct ICP_PIC_S {
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// -------- ICP_PIC_IRQ_RAWSTAT : (IRQ_RAWSTAT Offset: 0x04) IRQ raw interrupt status --------
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// -------- ICP_PIC_IRQ_ENABLESET : (IRQ_ENABLESET Offset: 0x08) IRQ enable set --------
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// -------- ICP_PIC_IRQ_ENABLECLR : (IRQ_ENABLECLR Offset: 0x0C) IRQ enable clear --------
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#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask
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#define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt
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#define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt
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#define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt
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#define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt
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#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask
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#define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt
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#define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt
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#define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt
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#define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt
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// -------- ICP_PIC_INT_SOFTSET : (INT_SOFTSET Offset: 0x10) Software interrupt set --------
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// -------- ICP_PIC_INT_SOFTCLR : (INT_SOFTCLR Offset: 0x14) Software interrupt clear --------
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/* module definitions */
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#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000
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#define BOARD_BASE_ADDRESS_PIC 0x14000000
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#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000
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#define BOARD_BASE_ADDRESS_PIC 0x14000000
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extern ICP_TIMER_T* const board_timer_0 ;
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extern ICP_PIC_T* const board_pic ;
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@@ -5,10 +5,6 @@
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.extern __fiq_stack_top__
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.extern __svc_stack_top__
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.global bsp_ints_enable
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.global bsp_ints_disable
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.global bsp_ints_restore
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.equ USR_MODE, 0x10
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.equ FIQ_MODE, 0x11
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@@ -49,13 +49,13 @@ GPTM_TIMER_T * const board_gptm0 = (GPTM_TIMER_T*)
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void
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dbg_format_msg (char *format, ...)
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{
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va_list args;
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static char msg[256] ;
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va_list args;
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static char msg[256] ;
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CRITICAL_STORE ;
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va_start (args, format) ;
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CRITICAL_START() ;
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vsnprintf ((char*)msg, 256, (char*)format, args) ;
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vsnprintf ((char*)msg, 256, (char*)format, args) ;
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printf (msg) ;
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CRITICAL_END() ;
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@@ -92,7 +92,7 @@ low_level_init (void)
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/**
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* \b __context_preempt_handler
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* \b __context_tick_handler
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*
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* System timer tic interupt handler.
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*
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@@ -113,44 +113,50 @@ __context_tick_handler (void)
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}
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/**
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* \b dbg_hard_fault_handler_c
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*
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* Dumps the registers pushed on the stack after a fault.
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*
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*/
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void
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dbg_hard_fault_handler_c (unsigned int * hardfault_args)
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{
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unsigned int stacked_r0;
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unsigned int stacked_r1;
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unsigned int stacked_r2;
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unsigned int stacked_r3;
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unsigned int stacked_r12;
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unsigned int stacked_lr;
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unsigned int stacked_pc;
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unsigned int stacked_psr;
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stacked_r0 = ((unsigned long) hardfault_args[0]);
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stacked_r1 = ((unsigned long) hardfault_args[1]);
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stacked_r2 = ((unsigned long) hardfault_args[2]);
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stacked_r3 = ((unsigned long) hardfault_args[3]);
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stacked_r12 = ((unsigned long) hardfault_args[4]);
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stacked_lr = ((unsigned long) hardfault_args[5]);
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stacked_pc = ((unsigned long) hardfault_args[6]);
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stacked_psr = ((unsigned long) hardfault_args[7]);
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printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n");
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printf ("SP = 0x%x\r\n", hardfault_args);
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printf ("R0 = 0x%x\r\n", stacked_r0);
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printf ("R1 = 0x%x\r\n", stacked_r1);
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printf ("R2 = 0x%x\r\n", stacked_r2);
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printf ("R3 = 0x%x\r\n", stacked_r3);
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printf ("R12 = 0x%x\r\n", stacked_r12);
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printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr);
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printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc);
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printf ("PSR = 0x%x\r\n", stacked_psr);
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//printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38))));
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//printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28))));
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//printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C))));
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//printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30))));
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//printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C))));
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// printf ("SCB_SHCSR = %x\n", SCB->SHCSR);
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unsigned int stacked_r0;
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unsigned int stacked_r1;
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unsigned int stacked_r2;
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unsigned int stacked_r3;
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unsigned int stacked_r12;
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unsigned int stacked_lr;
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unsigned int stacked_pc;
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unsigned int stacked_psr;
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stacked_r0 = ((unsigned long) hardfault_args[0]);
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stacked_r1 = ((unsigned long) hardfault_args[1]);
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stacked_r2 = ((unsigned long) hardfault_args[2]);
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stacked_r3 = ((unsigned long) hardfault_args[3]);
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stacked_r12 = ((unsigned long) hardfault_args[4]);
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stacked_lr = ((unsigned long) hardfault_args[5]);
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stacked_pc = ((unsigned long) hardfault_args[6]);
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stacked_psr = ((unsigned long) hardfault_args[7]);
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printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n");
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printf ("SP = 0x%x\r\n", hardfault_args);
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printf ("R0 = 0x%x\r\n", stacked_r0);
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printf ("R1 = 0x%x\r\n", stacked_r1);
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printf ("R2 = 0x%x\r\n", stacked_r2);
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printf ("R3 = 0x%x\r\n", stacked_r3);
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printf ("R12 = 0x%x\r\n", stacked_r12);
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printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr);
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printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc);
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printf ("PSR = 0x%x\r\n", stacked_psr);
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//printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38))));
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//printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28))));
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//printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C))));
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//printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30))));
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//printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C))));
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// printf ("SCB_SHCSR = %x\n", SCB->SHCSR);
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while (1);
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@@ -46,26 +46,26 @@ typedef volatile unsigned char REG_BYTE ;
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// *****************************************************************************
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typedef struct GPTM_TIMER_S {
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// offset read/write reset Description
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REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345
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REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346
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REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348
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REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350
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REG_DWORD Reserved[2] ; // 0x010
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REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353
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REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355
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REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356
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REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357
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REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359
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REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360
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REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361
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REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362
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REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363
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REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364
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REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365
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REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366
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REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367
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REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368
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// offset read/write reset Description
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REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345
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REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346
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REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348
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REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350
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REG_DWORD Reserved[2] ; // 0x010
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REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353
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REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355
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REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356
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REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357
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REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359
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REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360
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REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361
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REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362
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REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363
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REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364
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REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365
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REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366
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REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367
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REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368
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} GPTM_TIMER_T, *PGPTM_TIMER_T ;
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@@ -81,36 +81,36 @@ typedef struct GPTM_TIMER_S {
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#define GPTM_TIMER_TMR_TMR_PERIODIC ((unsigned int)0x02 << 0) // Periodic Timer mode
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#define GPTM_TIMER_TMR_TMR_CAPTURE ((unsigned int)0x03 << 0) // Capture mode
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// -------- GPTM_TIMER_CTL : (CTL Offset: 0x0C) This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration --------
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#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted.
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#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled.
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#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode
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#define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge
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#define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge
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#define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges
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#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger
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#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable
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// --------
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#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted.
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#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled.
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#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable
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#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode
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#define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge
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#define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge
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#define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges
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#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger
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#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable
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#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted.
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#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled.
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#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode
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#define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge
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#define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge
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#define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges
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#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger
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#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable
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// -------- //
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#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted.
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#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled.
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#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable
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#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode
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#define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge
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#define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge
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#define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges
|
||||
#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger
|
||||
#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable
|
||||
// -------- GPTM_TIMER_IMR : (IMR Offset: 0x18) This register allows software to enable/disable GPTM controller-level interrupts. --------
|
||||
// -------- GPTM_TIMER_RIS : (RIS Offset: 0x1C) This register shows the state of the GPTM's internal interrupt signal. --------
|
||||
// -------- GPTM_TIMER_MIS : (MIS Offset: 0x20) This register show the state of the GPTM's controller-level interrupt. --------
|
||||
// -------- GPTM_TIMER_ICR : (ICR Offset: 0x24) This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. --------
|
||||
#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask
|
||||
#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask
|
||||
#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask
|
||||
// --------
|
||||
#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask
|
||||
#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask
|
||||
#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask
|
||||
#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask
|
||||
#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask
|
||||
#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask
|
||||
#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask
|
||||
// -------- //
|
||||
#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask
|
||||
#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask
|
||||
#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask
|
||||
#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask
|
||||
|
||||
|
||||
|
||||
@@ -131,10 +131,10 @@ typedef struct SYSTICK_S {
|
||||
} SYSTICK_T, *PSYSTICK_T ;
|
||||
|
||||
// -------- SYSTICK_STCTRL : (STCTRL Offset: 0xE000E010) SysTick Control and Status Register --------
|
||||
#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read.
|
||||
#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock
|
||||
#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0.
|
||||
#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way.
|
||||
#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read.
|
||||
#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock
|
||||
#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0.
|
||||
#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way.
|
||||
// -------- SYSTICK_STRELOAD : (STRELOAD Offset: 0xE000E014) Reload Value --------
|
||||
#define SYSTICK_STRELOAD_MASK ((unsigned int)0xFFFFFF << 0) // IRQ mask
|
||||
// -------- SYSTICK_STCURRENT : (STCURRENT Offset: 0xE000E018) SysTick Current Value Register --------
|
||||
@@ -155,7 +155,7 @@ typedef struct NVIC_S {
|
||||
REG_DWORD Res6[30] ; // 0xE000E2A0
|
||||
REG_DWORD IABR[2] ; // 0xE000E300
|
||||
REG_DWORD Res7[64] ; // 0xE000E320
|
||||
REG_DWORD IPR[2] ; // 0xE000E400
|
||||
REG_DWORD IPR[2] ; // 0xE000E400
|
||||
// REG_DWORD Res7[515] ; // 0xE000E4F4
|
||||
|
||||
} NVIC_T, *PNVIC_T ;
|
||||
@@ -192,15 +192,15 @@ typedef struct SCB_S {
|
||||
|
||||
|
||||
/* module definitions */
|
||||
#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000
|
||||
#define BOARD_BASE_ADDRESS_NVIC 0xE000E100
|
||||
#define BOARD_BASE_ADDRESS_SCB 0xE000ED00
|
||||
#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000
|
||||
#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000
|
||||
#define BOARD_BASE_ADDRESS_NVIC 0xE000E100
|
||||
#define BOARD_BASE_ADDRESS_SCB 0xE000ED00
|
||||
#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000
|
||||
|
||||
extern SYSTICK_T* const board_systick ;
|
||||
extern NVIC_T* const board_nvic ;
|
||||
extern SCB_T* const board_scb ;
|
||||
extern GPTM_TIMER_T* const board_gptm0 ;
|
||||
extern SYSTICK_T* const board_systick ;
|
||||
extern NVIC_T* const board_nvic ;
|
||||
extern SCB_T* const board_scb ;
|
||||
extern GPTM_TIMER_T* const board_gptm0 ;
|
||||
|
||||
|
||||
/* Function prototypes */
|
||||
|
||||
Reference in New Issue
Block a user