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mz-startup
| Author | SHA1 | Date | |
|---|---|---|---|
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b0705e54ab | ||
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459e3f09ea |
@@ -1,8 +1,9 @@
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#
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# Startup code for Microchip PIC32 microcontrollers.
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# Using HID bootloader.
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# Based on the MIPS application note:
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# "Boot-CPS: Example Boot Code for MIPS® Cores".
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#
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# Copyright (C) 2010 Serge Vakulenko, <serge@vak.ru>
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# Copyright (C) 2010-2014 Serge Vakulenko, <serge@vak.ru>
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#
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# Permission to use, copy, modify, and distribute this software
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# and its documentation for any purpose and without fee is hereby
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@@ -26,6 +27,43 @@
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#define UBASE 0x7f008000 /* User space base address */
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/*
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* MIPS Coprocessor 0 register numbers
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*/
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#define C0_INDEX $0
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#define C0_ENTRYLO0 $2
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#define C0_ENTRYLO1 $3
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#define C0_PAGEMASK $5
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#define C0_WIRED $6
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#define C0_COUNT $9
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#define C0_ENTRYHI $10
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#define C0_COMPARE $11
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#define C0_STATUS $12
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#define C0_SRSCTL $12,2
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#define C0_CAUSE $13
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#define C0_EPC $14
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#define C0_CONFIG $16
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#define C0_CONFIG1 $16,1
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#define C0_CONFIG7 $16,7
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#define C0_WATCHLO $18
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#define C0_WATCHHI $19
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#define C0_DEBUG $23
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#define C0_DEPC $24
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#define C0_ITAGLO $28
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#define C0_DTAGLO $28,2
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#define C0_ERRPC $30
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/*
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* MIPS Config1 register
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*/
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#define CFG1_MMUSSHIFT 25 // mmu size - 1
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#define CFG1_ISSHIFT 22 // icache lines 64<<n
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#define CFG1_ILSHIFT 19 // icache line size 2<<n
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#define CFG1_IASHIFT 16 // icache ways - 1
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#define CFG1_DSSHIFT 13 // dcache lines 64<<n
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#define CFG1_DLSHIFT 10 // dcache line size 2<<n
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#define CFG1_DASHIFT 7 // dcache ways - 1
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.set noreorder
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.set mips32r2
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.set nomips16
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@@ -45,52 +83,279 @@
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_reset_vector_: .globl _reset_vector_
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.set noat
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move $1, $zero # Clear all regs
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move $2, $zero
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move $3, $zero
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move $4, $zero
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move $5, $zero
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move $6, $zero
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move $7, $zero
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move $8, $zero
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move $9, $zero
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move $10, $zero
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move $11, $zero
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move $12, $zero
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move $13, $zero
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move $14, $zero
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move $15, $zero
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move $16, $zero
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move $17, $zero
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move $18, $zero
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move $19, $zero
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move $20, $zero
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move $21, $zero
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move $22, $zero
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move $23, $zero
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move $24, $zero
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move $25, $zero
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move $26, $zero
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move $27, $zero
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move $28, $zero
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move $29, $zero
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move $30, $zero
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move $31, $zero
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mtlo $zero
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mthi $zero
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.set at
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mtc0 $0, C0_COUNT # Clear cp0 Count (Used to measure boot time.)
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#if 0
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//
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// Check for NMI exception.
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//
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check_nmi: # Check whether we are here due to a reset or NMI.
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mfc0 $s1, C0_STATUS # Read Status
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ext $s1, $s1, 19, 1 # extract NMI
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beqz $s1, init_gpr # Branch if this is NOT an NMI exception.
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nop
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# Call nmi_exception().
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la $sp, _stack-16 # Set up stack base.
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la $gp, _gp # GP register value defined by linker script.
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la $s1, nmi_exception # Call user-defined NMI handler.
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jalr $s1
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nop
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#endif
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//
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// Set all GPRs of all register sets to predefined state.
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//
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init_gpr:
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li $1, 0xdeadbeef # 0xdeadbeef stands out, kseg2 mapped, odd.
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# Determine how many shadow sets are implemented (in addition to the base register set.)
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# the first time thru the loop it will initialize using $1 set above.
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# At the bottom og the loop, 1 is subtract from $30
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# and loop back to next_shadow_set to start the next loop and the next lowest set number.
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mfc0 $29, C0_SRSCTL # read SRSCtl
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ext $30, $29, 26, 4 # extract HSS
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next_shadow_set: # set PSS to shadow set to be initialized
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ins $29, $30, 6, 4 # insert PSS
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mtc0 $29, C0_SRSCTL # write SRSCtl
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wrpgpr $1, $1
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wrpgpr $2, $1
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wrpgpr $3, $1
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wrpgpr $4, $1
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wrpgpr $5, $1
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wrpgpr $6, $1
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wrpgpr $7, $1
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wrpgpr $8, $1
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wrpgpr $9, $1
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wrpgpr $10, $1
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wrpgpr $11, $1
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wrpgpr $12, $1
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wrpgpr $13, $1
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wrpgpr $14, $1
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wrpgpr $15, $1
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wrpgpr $16, $1
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wrpgpr $17, $1
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wrpgpr $18, $1
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wrpgpr $19, $1
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wrpgpr $20, $1
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wrpgpr $21, $1
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wrpgpr $22, $1
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wrpgpr $23, $1
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wrpgpr $24, $1
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wrpgpr $25, $1
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wrpgpr $26, $1
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wrpgpr $27, $1
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wrpgpr $28, $1
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beqz $30, init_cp0
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wrpgpr $29, $1
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wrpgpr $30, $1
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wrpgpr $31, $1
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b next_shadow_set
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add $30, -1 # Decrement to the next lower number
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//
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// Init CP0 Status, Count, Compare, Watch*, and Cause.
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//
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init_cp0:
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# Initialize Status
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li $v1, 0x00400404 # (M_StatusIM | M_StatusERL | M_StatusBEV)
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mtc0 $v1, C0_STATUS # write Status
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# Initialize Watch registers if implemented.
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mfc0 $v0, C0_CONFIG1 # read Config1
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ext $v1, $v0, 3, 1 # extract bit 3 WR (Watch registers implemented)
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beq $v1, $zero, done_wr
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li $v1, 0x7 # (M_WatchHiI | M_WatchHiR | M_WatchHiW)
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# Clear Watch Status bits and disable watch exceptions
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mtc0 $v1, C0_WATCHHI # write WatchHi0
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mfc0 $v0, C0_WATCHHI # read WatchHi0
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bgez $v0, done_wr # Check for bit 31 (sign bit) for more Watch registers
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mtc0 $zero, C0_WATCHLO # clear WatchLo0
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mtc0 $v1, C0_WATCHHI, 1 # write WatchHi1
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mfc0 $v0, C0_WATCHHI, 1 # read WatchHi1
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bgez $v0, done_wr # Check for bit 31 (sign bit) for more Watch registers
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mtc0 $zero, C0_WATCHLO, 1 # clear WatchLo1
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mtc0 $v1, C0_WATCHHI, 2 # write WatchHi2
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mfc0 $v0, C0_WATCHHI, 2 # read WatchHi2
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bgez $v0, done_wr # Check for bit 31 (sign bit) for more Watch registers
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mtc0 $zero, C0_WATCHLO, 2 # clear WatchLo2
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mtc0 $v1, C0_WATCHHI, 3 # write WatchHi3
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mfc0 $v0, C0_WATCHHI, 3 # read WatchHi3
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bgez $v0, done_wr # Check for bit 31 (sign bit) for more Watch registers
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mtc0 $zero, C0_WATCHLO, 3 # clear WatchLo3
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mtc0 $v1, C0_WATCHHI, 4 # write WatchHi4
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mfc0 $v0, C0_WATCHHI, 4 # read WatchHi4
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bgez $v0, done_wr # Check for bit 31 (sign bit) for more Watch registers
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mtc0 $zero, C0_WATCHLO, 4 # clear WatchLo4
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mtc0 $v1, C0_WATCHHI, 5 # write WatchHi5
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mfc0 $v0, C0_WATCHHI, 5 # read WatchHi5
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bgez $v0, done_wr # Check for bit 31 (sign bit) for more Watch registers
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mtc0 $zero, C0_WATCHLO, 5 # clear WatchLo5
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mtc0 $v1, C0_WATCHHI, 6 # write WatchHi6
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mfc0 $v0, C0_WATCHHI, 6 # read WatchHi6
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bgez $v0, done_wr # Check for bit 31 (sign bit) for more Watch registers
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mtc0 $zero, C0_WATCHLO, 6 # clear WatchLo6
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mtc0 $v1, C0_WATCHHI, 7 # write WatchHi7
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mtc0 $zero, C0_WATCHLO, 7 # clear WatchLo7
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done_wr:
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# Clear WP bit to avoid watch exception upon user code entry, IV, and software interrupts.
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mtc0 $zero, C0_CAUSE # clear Cause: init AFTER init of WatchHi/Lo registers.
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# Clear timer interrupt. (Count was cleared at the reset vector to allow timing boot.)
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b init_tlb # Jump over exception vectors
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mtc0 $zero, C0_COMPARE # clear Compare
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//
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// Clear TLB: generate unique EntryHi contents per entry pair.
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//
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init_tlb:
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# Determine if we have a TLB
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mfc0 $v1, C0_CONFIG # read Config
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ext $v1, $v1, 7, 3 # extract MT field
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li $a3, 0x1 # load a 1 to check against
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bne $v1, $a3, init_icache
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# Config1MMUSize == Number of TLB entries - 1
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mfc0 $v0, C0_CONFIG1 # Config1
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ext $v1, $v0, CFG1_MMUSSHIFT, 6 # extract MMU Size
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mtc0 $zero, C0_ENTRYLO0 # clear EntryLo0
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mtc0 $zero, C0_ENTRYLO1 # clear EntryLo1
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mtc0 $zero, C0_PAGEMASK # clear PageMask
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mtc0 $zero, C0_WIRED # clear Wired
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li $a0, 0x80000000
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next_tlb_entry:
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mtc0 $v1, C0_INDEX # write Index
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mtc0 $a0, C0_ENTRYHI # write EntryHi
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ehb
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tlbwi
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add $a0, 2<<13 # Add 8K to the address to avoid TLB conflict with previous entry
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bne $v1, $zero, next_tlb_entry
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add $v1, -1
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//
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// Clear L1 instruction cache.
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//
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init_icache:
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# Determine how big the I-cache is
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mfc0 $v0, C0_CONFIG1 # read Config1
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ext $v1, $v0, CFG1_ILSHIFT, 3 # extract I-cache line size
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beq $v1, $zero, done_icache # Skip ahead if no I-cache
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nop
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mfc0 $s1, C0_CONFIG7 # Read Config7
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ext $s1, $s1, 18, 1 # extract HCI
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bnez $s1, done_icache # Skip when Hardware Cache Initialization bit set
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li $a2, 2
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sllv $v1, $a2, $v1 # Now have true I-cache line size in bytes
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ext $a0, $v0, CFG1_ISSHIFT, 3 # extract IS
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li $a2, 64
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sllv $a0, $a2, $a0 # I-cache sets per way
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ext $a1, $v0, CFG1_IASHIFT, 3 # extract I-cache Assoc - 1
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add $a1, 1
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mul $a0, $a0, $a1 # Total number of sets
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lui $a2, 0x8000 # Get a KSeg0 address for cacheops
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mtc0 $zero, C0_ITAGLO # Clear ITagLo register
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move $a3, $a0
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next_icache_tag:
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# Index Store Tag Cache Op
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# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
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cache 0x8, 0($a2) # ICIndexStTag
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add $a3, -1 # Decrement set counter
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bne $a3, $zero, next_icache_tag
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add $a2, $v1 # Get next line address
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done_icache:
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//
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// Enable cacheability of kseg0 segment.
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// Need to switch to kseg1, modify kseg0 CCA, then switch back.
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//
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la $a2, enable_k0_cache
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li $a1, 0xf
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ins $a2, $a1, 29, 1 # changed to KSEG1 address by setting bit 29
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jr $a2
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nop
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enable_k0_cache:
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# Set CCA for kseg0 to cacheable.
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# NOTE! This code must be executed in KSEG1 (not KSEG0 uncached)
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mfc0 $v0, C0_CONFIG # read C0_Config
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li $v1, 3 # CCA for single-core processors
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ins $v0, $v1, 0, 3 # instert K0
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mtc0 $v0, C0_CONFIG # write C0_Config
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la $a2, init_dcache
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jr $a2 # switch back to KSEG0
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ehb
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//
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// Initialize the L1 data cache
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//
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init_dcache:
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mfc0 $v0, C0_CONFIG1 # read C0_Config1
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ext $v1, $v0, CFG1_DLSHIFT, 3 # extract D-cache line size
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beq $v1, $zero, done_dcache # Skip ahead if no D-cache
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nop
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mfc0 $s1, C0_CONFIG7 # Read Config7
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ext $s1, $s1, 18, 1 # extract HCI
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bnez $s1, done_dcache # Skip when Hardware Cache Initialization bit set
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li $a2, 2
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sllv $v1, $a2, $v1 # Now have true D-cache line size in bytes
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ext $a0, $v0, CFG1_DSSHIFT, 3 # extract DS
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li $a2, 64
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sllv $a0, $a2, $a0 # D-cache sets per way
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ext $a1, $v0, CFG1_DASHIFT, 3 # extract D-cache Assoc - 1
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add $a1, 1
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mul $a0, $a0, $a1 # Get total number of sets
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lui $a2, 0x8000 # Get a KSeg0 address for cacheops
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mtc0 $zero, C0_ITAGLO # Clear ITagLo/DTagLo registers
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mtc0 $zero, C0_DTAGLO
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move $a3, $a0
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next_dcache_tag:
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# Index Store Tag Cache Op
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# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
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cache 0x9, 0($a2) # DCIndexStTag
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add $a3, -1 # Decrement set counter
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bne $a3, $zero, next_dcache_tag
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add $a2, $v1 # Get next line address
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done_dcache:
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//
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// Call main() function.
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//
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la $sp, u_end - 16 # Stack at end of U area
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la $a0, main
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jalr $a0 # Jump to main()
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lui $gp, 0x8000 # Set global pointer (delay slot)
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la $k0, UBASE
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mtc0 $k0, $C0_EPC # Entry to user code.
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mtc0 $k0, C0_EPC # Entry to user code.
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mfc0 $k0, $C0_STATUS
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mfc0 $k0, C0_STATUS
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ori $k0, $k0, ST_UM | ST_EXL | ST_IE # Set user mode and enable interrupts
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mtc0 $k0, $C0_STATUS # Put SR back
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mtc0 $k0, C0_STATUS # Put SR back
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ehb
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eret # PC <= EPC; EXL <= 0
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nop # just to be safe
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@@ -116,7 +381,7 @@ _entry_vector_: .globl _entry_vector_
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.type _exception_vector_, @function
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_exception_vector_: .globl _exception_vector_
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mfc0 $k0, $C0_STATUS
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mfc0 $k0, C0_STATUS
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andi $k1, $k0, ST_UM # Check user mode
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beqz $k1, kernel_exception
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move $k1, $sp
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@@ -172,7 +437,7 @@ save_regs:
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mflo $k0
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sw $k0, (16+FRAME_LO*4) ($sp)
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mfc0 $k0, $C0_EPC
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mfc0 $k0, C0_EPC
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sw $k0, (16+FRAME_PC*4) ($sp)
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move $a0, $sp
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@@ -225,11 +490,11 @@ restore_regs:
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# Do not use k0/k1 here, as interrupts are still enabled
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lw $31, (16+FRAME_STATUS*4) ($sp) # K0 = saved status
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ori $31, ST_EXL # Set EXL
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mtc0 $31, $C0_STATUS # put SR back: disable interrupts
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mtc0 $31, C0_STATUS # put SR back: disable interrupts
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ehb
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lw $k0, (16+FRAME_PC*4) ($sp) # K0 = EPC
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mtc0 $k0, $C0_EPC # put PC in EPC
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||||
mtc0 $k0, C0_EPC # put PC in EPC
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ext $k1, $31, 27, 1 # get RP bit: single-step request
|
||||
|
||||
lw $31, (16+FRAME_RA*4) ($sp)
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@@ -249,39 +514,39 @@ debug_request:
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.type _debug_vector_, @function
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_debug_vector_: .globl _debug_vector_
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|
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mfc0 $k0, $C0_DEPC
|
||||
mfc0 $k0, C0_DEPC
|
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la $k1, debug_request
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bne $k0, $k1, single_step_done
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||||
nop
|
||||
|
||||
# single step request
|
||||
mfc0 $k0, $C0_DEBUG
|
||||
mfc0 $k0, C0_DEBUG
|
||||
ori $k0, DB_SST # set SST bit
|
||||
mtc0 $k0, $C0_DEBUG
|
||||
mtc0 $k0, C0_DEBUG
|
||||
|
||||
mfc0 $k1, $C0_EPC
|
||||
mtc0 $k1, $C0_DEPC # DEPC <= EPC
|
||||
mfc0 $k0, $C0_STATUS
|
||||
mfc0 $k1, C0_EPC
|
||||
mtc0 $k1, C0_DEPC # DEPC <= EPC
|
||||
mfc0 $k0, C0_STATUS
|
||||
xori $k0, ST_EXL # Clear EXL
|
||||
mtc0 $k0, $C0_STATUS
|
||||
mtc0 $k0, C0_STATUS
|
||||
ehb
|
||||
deret # PC <= DEPC; DM <= 0
|
||||
|
||||
single_step_done:
|
||||
mtc0 $k0, $C0_EPC # EPC <= DEPC
|
||||
mtc0 $k0, C0_EPC # EPC <= DEPC
|
||||
|
||||
la $k1, _exception_vector_
|
||||
mtc0 $k1, $C0_DEPC # DEPC <= exception handler
|
||||
mtc0 $k1, C0_DEPC # DEPC <= exception handler
|
||||
|
||||
mfc0 $k0, $C0_DEBUG
|
||||
mfc0 $k0, C0_DEBUG
|
||||
sw $k0, c0_debug # save Debug register
|
||||
ori $k0, DB_SST
|
||||
xori $k0, DB_SST # clear SST bit
|
||||
mtc0 $k0, $C0_DEBUG
|
||||
mtc0 $k0, C0_DEBUG
|
||||
|
||||
mfc0 $k1, $C0_STATUS
|
||||
mfc0 $k1, C0_STATUS
|
||||
ori $k1, ST_EXL # Set EXL
|
||||
mtc0 $k1, $C0_STATUS
|
||||
mtc0 $k1, C0_STATUS
|
||||
ehb
|
||||
deret # PC <= DEPC; DM <= 0
|
||||
|
||||
|
||||
@@ -27,6 +27,7 @@
|
||||
/*--------------------------------------
|
||||
* Coprocessor 0 registers.
|
||||
*/
|
||||
#ifndef __ASSEMBLER__
|
||||
#define C0_HWRENA 7 /* Enable RDHWR in non-privileged mode */
|
||||
#define C0_BADVADDR 8 /* Virtual address of last exception */
|
||||
#define C0_COUNT 9 /* Processor cycle count */
|
||||
@@ -47,6 +48,7 @@
|
||||
#define C0_DEPC 24 /* Program counter at last debug exception */
|
||||
#define C0_ERROREPC 30 /* Program counter at last error */
|
||||
#define C0_DESAVE 31 /* Debug handler scratchpad register */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Status register.
|
||||
|
||||
@@ -1684,7 +1684,8 @@ static int rdpgpr_op (cpu_mips_t * cpu, mips_insn_t insn)
|
||||
int rt = bits (insn, 16, 20);
|
||||
int rd = bits (insn, 11, 15);
|
||||
|
||||
printf ("%08x: unsupported RDPGPR $%u,$%u instruction.\n", cpu->pc, rd, rt);
|
||||
/* Only one GPR set supported: RDPGPR works as move. */
|
||||
cpu->reg_set (cpu, rd, cpu->gpr[rt]);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@@ -1693,7 +1694,8 @@ static int wrpgpr_op (cpu_mips_t * cpu, mips_insn_t insn)
|
||||
int rt = bits (insn, 16, 20);
|
||||
int rd = bits (insn, 11, 15);
|
||||
|
||||
printf ("%08x: unsupported WRPGPR $%u,$%u instruction.\n", cpu->pc, rd, rt);
|
||||
/* Only one GPR set supported: WRPGPR works as move. */
|
||||
cpu->reg_set (cpu, rd, cpu->gpr[rt]);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
@@ -93,6 +93,8 @@ unimpl: fprintf (stderr,
|
||||
return cp0->reg[cp0_reg];
|
||||
case 1: /* IntCtl */
|
||||
return cp0->intctl_reg;
|
||||
case 2: /* SRSCtl */
|
||||
return 0;
|
||||
}
|
||||
goto unimpl;
|
||||
|
||||
@@ -172,6 +174,8 @@ void mips_cp0_set_reg (cpu_mips_t * cpu, u_int cp0_reg, u_int sel,
|
||||
case 1: /* IntCtl */
|
||||
cp0->intctl_reg = val;
|
||||
break;
|
||||
case 2: /* SRSCtl */
|
||||
break;
|
||||
default:
|
||||
goto unimpl;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user