dm36x: Write README file for DM365/DM368.

Also minor changes to AVR/STM8 ports to use similar code structure throughout all ports.

README

@@ -1,7 +1,7 @@
 ---------------------------------------------------------------------------
 
 Library:      Atomthreads
-Author:       Kelvin Lawson <kelvinl@users.sf.net>
+Author:       Kelvin Lawson <info@atomthreads.com>
 Website:      http://atomthreads.com
 License:      BSD Revised
 

kernel/README

@@ -1,11 +1,11 @@
----------------------------------------------------------------------------
+---------------------------------------------------------------------------
-
+
-Library:      Atomthreads
+Library:      Atomthreads
-Author:       Kelvin Lawson <kelvinl@users.sf.net>
+Author:       Kelvin Lawson <info@atomthreads.com>
-Website:      http://atomthreads.com
+Website:      http://atomthreads.com
-License:      BSD Revised
+License:      BSD Revised
-
+
----------------------------------------------------------------------------
+---------------------------------------------------------------------------
 
 KERNEL SOURCES
 
@@ -21,12 +21,12 @@ Each module source file contains detailed documentation including an
 introduction to usage of the module and full descriptions of each API.
 Refer to the sources for further documentation.
 
----------------------------------------------------------------------------
+---------------------------------------------------------------------------
 
 BUILDING THE KERNEL
 
 The kernel is built from the architecture port folder. Build instructions
 are included in the README file for each port.
 
----------------------------------------------------------------------------
+---------------------------------------------------------------------------
 

kernel/atom.h

@@ -30,6 +30,10 @@
 #ifndef __ATOM_H
 #define __ATOM_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include "atomtimer.h"
 #include "atomport.h"
 
@@ -40,8 +44,10 @@ struct atom_tcb;
 
 typedef struct atom_tcb
 {
-    /* Thread's current stack pointer. When a thread is scheduled
+    /*
-     * out the architecture port can save*/
+     * Thread's current stack pointer. When a thread is scheduled
+     * out the architecture port can save its stack pointer here.
+     */
     POINTER sp_save_ptr;
 
     /* Thread priority (0-255) */
@@ -62,7 +68,7 @@ typedef struct atom_tcb
 
     /* Details used if thread stack-checking is required */
 #ifdef ATOM_STACK_CHECKING
-    POINTER stack_top;            /* Pointer to top of stack allocation */
+    POINTER stack_bottom;         /* Pointer to bottom of stack allocation */
     uint32_t stack_size;          /* Size of stack allocation in bytes */
 #endif
 
@@ -98,7 +104,7 @@ extern uint8_t atomOSStarted;
 
 
 /* Function prototypes */
-extern uint8_t atomOSInit (void *idle_thread_stack_top, uint32_t stack_size);
+extern uint8_t atomOSInit (void *idle_thread_stack_bottom, uint32_t idle_thread_stack_size, uint8_t idle_thread_stack_check);
 extern void atomOSStart (void);
 
 extern void atomSched (uint8_t timer_tick);
@@ -113,7 +119,7 @@ extern ATOM_TCB *tcbDequeuePriority (ATOM_TCB **tcb_queue_ptr, uint8_t priority)
 
 extern ATOM_TCB *atomCurrentContext (void);
 
-extern uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_point)(uint32_t), uint32_t entry_param, void *stack_top, uint32_t stack_size);
+extern uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_point)(uint32_t), uint32_t entry_param, void *stack_bottom, uint32_t stack_size, uint8_t stack_check);
 extern uint8_t atomThreadStackCheck (ATOM_TCB *tcb_ptr, uint32_t *used_bytes, uint32_t *free_bytes);
 
 extern void archContextSwitch (ATOM_TCB *old_tcb_ptr, ATOM_TCB *new_tcb_ptr);
@@ -122,5 +128,8 @@ extern void archFirstThreadRestore(ATOM_TCB *new_tcb_ptr);
 
 extern void atomTimerTick (void);
 
+#ifdef __cplusplus
+}
+#endif
 
 #endif /* __ATOM_H */

kernel/atomkernel.c

@@ -28,7 +28,7 @@
  */
 
 
-/** 
+/**
  * \file
  * Kernel library.
  *
@@ -114,7 +114,7 @@
  * run since the thread was created. The context-save area is formatted in
  * exactly the same manner.
  *
- * 
+ *
  * \b Functions contained in this module:\n
  *
  * \b Application-callable initialisation functions: \n
@@ -144,7 +144,6 @@
  */
 
 
-#include <stddef.h>
 #include "atom.h"
 
 
@@ -370,25 +369,31 @@ static void atomThreadSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb)
  * new thread may be scheduled in before the function returns.
  *
  * Optionally prefills the thread stack with a known value to enable stack
- * usage checking (if the ATOM_STACK_CHECKING macro is defined).
+ * usage checking (if the ATOM_STACK_CHECKING macro is defined and
+ * stack_check parameter is set to TRUE).
  *
  * @param[in] tcb_ptr Pointer to the thread's TCB storage
  * @param[in] priority Priority of the thread (0 to 255)
  * @param[in] entry_point Thread entry point
  * @param[in] entry_param Parameter passed to thread entry point
- * @param[in] stack_top Top of the stack area
+ * @param[in] stack_bottom Bottom of the stack area
  * @param[in] stack_size Size of the stack area in bytes
+ * @param[in] stack_check TRUE to enable stack checking for this thread
  *
  * @retval ATOM_OK Success
  * @retval ATOM_ERR_PARAM Bad parameters
  * @retval ATOM_ERR_QUEUE Error putting the thread on the ready queue
  */
-uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_point)(uint32_t), uint32_t entry_param, void *stack_top, uint32_t stack_size)
+uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_point)(uint32_t), uint32_t entry_param, void *stack_bottom, uint32_t stack_size, uint8_t stack_check)
 {
     CRITICAL_STORE;
     uint8_t status;
+    uint8_t *stack_top;
+#ifdef ATOM_STACK_CHECKING
+	int32_t count;
+#endif
 
-    if ((tcb_ptr == NULL) || (entry_point == NULL) || (stack_top == NULL)
+    if ((tcb_ptr == NULL) || (entry_point == NULL) || (stack_bottom == NULL)
         || (stack_size == 0))
     {
         /* Bad parameters */
@@ -412,6 +417,13 @@ uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_poin
         tcb_ptr->entry_point = entry_point;
         tcb_ptr->entry_param = entry_param;
 
+        /**
+         * Calculate a pointer to the topmost stack entry, suitably aligned
+         * for the architecture. This may discard the top few bytes if the
+         * stack size is not a multiple of the stack entry/alignment size.
+         */
+        stack_top = (uint8_t *)stack_bottom + (stack_size & ~(STACK_ALIGN_SIZE - 1)) - STACK_ALIGN_SIZE;
+
         /**
          * Additional processing only required if stack-checking is
          * enabled. Incurs a slight overhead on each thread creation
@@ -419,25 +431,29 @@ uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_poin
          * compiled out if not desired.
          */
 #ifdef ATOM_STACK_CHECKING
-
+        /* Set up stack-checking if enabled for this thread */
-        /* Store the stack details for use by the stack-check function */
+        if (stack_check)
-        tcb_ptr->stack_top = stack_top;
-        tcb_ptr->stack_size = stack_size;
-
-        /**
-         * Prefill the stack with a known value. This is used later in
-         * calls to atomThreadStackCheck() to get an indication of how
-         * much stack has been used during runtime.
-         */
-        while (stack_size > 0)
         {
-            /* Initialise all stack bytes from bottom up to 0x5A */
+            /* Store the stack details for use by the stack-check function */
-            *((uint8_t *)stack_top - (stack_size - 1)) = STACK_CHECK_BYTE;
+            tcb_ptr->stack_bottom = stack_bottom;
-            stack_size--;
+            tcb_ptr->stack_size = stack_size;
+
+            /**
+             * Prefill the stack with a known value. This is used later in
+             * calls to atomThreadStackCheck() to get an indication of how
+             * much stack has been used during runtime.
+             */
+		    count = (int32_t)stack_size;
+            while (count > 0)
+            {
+                /* Initialise all stack bytes from top down to 0x5A */
+                *((uint8_t *)stack_bottom + (count - 1)) = STACK_CHECK_BYTE;
+                count--;
+            }
         }
 #else
-        /* Avoid compiler warnings due to unused stack_size variable */
+        /* Avoid compiler warning due to unused parameter */
-        stack_size = stack_size;
+        stack_check = stack_check;
 #endif
 
         /**
@@ -501,7 +517,7 @@ uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_poin
  * have strayed outside of the allowable stack area while leaving some of
  * the known-value bytes unmodified. This simple method cannot trap stack
  * usage outside of the thread's allocated stack, for which you could use
- * additional guard areas (still limited in scope) or compiler/CPU/MMU 
+ * additional guard areas (still limited in scope) or compiler/CPU/MMU
  * features.
  *
  * The function takes a thread's TCB and returns both the number of stack
@@ -529,10 +545,10 @@ uint8_t atomThreadStackCheck (ATOM_TCB *tcb_ptr, uint32_t *used_bytes, uint32_t
     else
     {
         /**
-         * Starting at the far end, count the unmodified areas until a
+         * Starting at the bottom end, count the unmodified areas until a
          * modified byte is found.
          */
-        stack_ptr = (uint8_t *)tcb_ptr->stack_top - (tcb_ptr->stack_size - 1);
+        stack_ptr = (uint8_t *)tcb_ptr->stack_bottom;
         for (i = 0; i < tcb_ptr->stack_size; i++)
         {
             /* Loop until a modified byte is found */
@@ -648,13 +664,14 @@ ATOM_TCB *atomCurrentContext (void)
  * operating system facilities are being initialised. They are normally
  * enabled by the archFirstThreadRestore() routine in the architecture port.
  *
- * @param[in] idle_thread_stack_top Ptr to top of stack area for idle thread
+ * @param[in] idle_thread_stack_bottom Ptr to bottom of stack for idle thread
  * @param[in] idle_thread_stack_size Size of idle thread stack in bytes
+ * @param[in] idle_thread_stack_check TRUE if stack checking required on idle thread
  *
  * @retval ATOM_OK Success
  * @retval ATOM_ERROR Initialisation error
  */
-uint8_t atomOSInit (void *idle_thread_stack_top, uint32_t idle_thread_stack_size)
+uint8_t atomOSInit (void *idle_thread_stack_bottom, uint32_t idle_thread_stack_size, uint8_t idle_thread_stack_check)
 {
     uint8_t status;
 
@@ -668,8 +685,9 @@ uint8_t atomOSInit (void *idle_thread_stack_top, uint32_t idle_thread_stack_size
                  IDLE_THREAD_PRIORITY,
                  atomIdleThread,
                  0,
-                 idle_thread_stack_top,
+                 idle_thread_stack_bottom,
-                 idle_thread_stack_size);
+                 idle_thread_stack_size,
+				 idle_thread_stack_check);
 
     /* Return status */
     return (status);

kernel/atommutex.c

@@ -101,7 +101,6 @@
  */
 
 
-#include <stdio.h>
 #include "atom.h"
 #include "atommutex.h"
 #include "atomtimer.h"

kernel/atommutex.h

@@ -29,6 +29,10 @@
 #ifndef __ATOM_MUTEX_H
 #define __ATOM_MUTEX_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 typedef struct atom_mutex
 {
     ATOM_TCB *  suspQ;  /* Queue of threads suspended on this mutex */
@@ -41,4 +45,8 @@ extern uint8_t atomMutexDelete (ATOM_MUTEX *mutex);
 extern uint8_t atomMutexGet (ATOM_MUTEX *mutex, int32_t timeout);
 extern uint8_t atomMutexPut (ATOM_MUTEX *mutex);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ATOM_MUTEX_H */

kernel/atomport-template.h

@@ -34,6 +34,15 @@
 /* Required number of system ticks per second (normally 100 for 10ms tick) */
 #define SYSTEM_TICKS_PER_SEC            100
 
+/**
+ * Definition of NULL.
+ * If stddef.h is available on the platform it is simplest to include it
+ * from this header, otherwise define below.
+ */
+#define NULL      ((void *)(0))
+
+/* Size of each stack entry / stack alignment size (e.g. 8 bits) */
+#define STACK_ALIGN_SIZE                sizeof(unsigned char)
 
 /**
  * Architecture-specific types.
@@ -51,7 +60,12 @@
 #define POINTER   void *
 
 
-/* Critical region protection */
+/**
+ * Critical region protection: this should disable interrupts
+ * to protect OS data structures during modification. It must
+ * allow nested calls, which means that interrupts should only
+ * be re-enabled when the outer CRITICAL_END() is reached.
+ */
 #define CRITICAL_STORE      uint8_t sreg
 #define CRITICAL_START()    sreg = SREG; cli();
 #define CRITICAL_END()      SREG = sreg

kernel/atomqueue.c

@@ -91,7 +91,6 @@
  */
  
 
-#include <stdio.h>
 #include <string.h>
 
 #include "atom.h"

kernel/atomqueue.h

@@ -29,6 +29,10 @@
 #ifndef __ATOM_QUEUE_H
 #define __ATOM_QUEUE_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 typedef struct atom_queue
 {
     ATOM_TCB *  putSuspQ;       /* Queue of threads waiting to send */
@@ -46,4 +50,8 @@ extern uint8_t atomQueueDelete (ATOM_QUEUE *qptr);
 extern uint8_t atomQueueGet (ATOM_QUEUE *qptr, int32_t timeout, uint8_t *msgptr);
 extern uint8_t atomQueuePut (ATOM_QUEUE *qptr, int32_t timeout, uint8_t *msgptr);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ATOM_QUEUE_H */

kernel/atomsem.c

@@ -88,7 +88,6 @@
  */
 
 
-#include <stdio.h>
 #include "atom.h"
 #include "atomsem.h"
 #include "atomtimer.h"

kernel/atomsem.h

@@ -30,6 +30,10 @@
 #ifndef __ATOM_SEM_H
 #define __ATOM_SEM_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 typedef struct atom_sem
 {
     ATOM_TCB *  suspQ;  /* Queue of threads suspended on this semaphore */
@@ -42,4 +46,8 @@ extern uint8_t atomSemGet (ATOM_SEM *sem, int32_t timeout);
 extern uint8_t atomSemPut (ATOM_SEM *sem);
 extern uint8_t atomSemResetCount (ATOM_SEM *sem, uint8_t count);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ATOM_SEM_H */

kernel/atomtimer.c

@@ -67,7 +67,6 @@
  */
 
 
-#include <stdio.h>
 #include "atom.h"
 
 

kernel/atomtimer.h

@@ -30,6 +30,10 @@
 #ifndef __ATOM_TIMER_H
 #define __ATOM_TIMER_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include "atomport.h"
 
 
@@ -58,4 +62,8 @@ extern uint8_t atomTimerDelay (uint32_t ticks);
 extern uint32_t atomTimeGet (void);
 extern void atomTimeSet (uint32_t new_time);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ATOM_TIMER_H */

ports/arm/README

@@ -0,0 +1,107 @@
+---------------------------------------------------------------------------
+
+Library:      Atomthreads ARM Port
+Author:       Natie van Rooyen <natie@navaro.nl>
+License:      BSD Revised
+
+---------------------------------------------------------------------------
+
+ARM PORT
+
+This folder contains a port of the Atomthreads real time kernel for the
+ARM processor architecture. This port was tested on the ARMv5 and ARMv7 
+architectures.
+
+The same common/core port can be used on a wide variety of ARM devices
+but platform-specific code has been separated out into multiple "platform"
+(BSP) folders. This allows the common ARM code to be shared among several
+different ARM platforms and boards. For example, different ARM devices and
+platforms might use different interrupt controllers, timer subsystems and
+UARTs but share the same core OS context-switching routines etc.
+
+An example platform is in the "platforms/qemu_integratorcp" folder. The
+platform-specific folders such as this contain the Makefile to build the
+project for that platform, so you may wish to head straight there if you
+wish to quickly get started building and running Atomthreads on ARM. The
+qemu_integratorcp platform is designed for the Integrator/CP platform with
+ARM926EJ-S processor, and can be run within QEMU for quick evaluation of
+Atomthreads without real hardware.
+
+
+---------------------------------------------------------------------------
+
+FILES IN THE COMMON ARM PORT FOLDER
+
+ * tests-main.c: Contains a sample Atomthreads application starting at
+   main() that initialises the operating system and runs the automated test
+   suite applications. You will normally make your own main() function
+   suitable for your application, possibly using this as a basis.
+ * atomport-asm.s: Contains the main assembler code that forms the portion
+   of the core ARM architecture port that must be implemented in assembler
+   (e.g. register save/restore for thread context-switching).
+ * atomport.c: Contains the main C code that forms the portion of the core
+   ARM architecture port that can be implemented in C (e.g. prefilling the
+   stack context for new threads).
+ * syscalls.c: Contains the open/close/read/write/heap-management
+   functions typically required if you want to do anything with stdio
+   (e.g. printf() calls etc). This is a very simple implementation that
+   always writes to the UART regardless of which file is "opened". Use of
+   printf() and friends with GCC toolchains typically requires a heap, and
+   thus a heap is supported in this file via the _sbrk() function. Your
+   linker script should specify where the heap starts and stops using "end"
+   and "heap_top" definitions respectively. Note that in QEMU environments
+   this may not be required as some "semi-hosted" toolchains implement
+   these functions and the UART driver for you. In that case these
+   functions will be left out of the build because they are defined with
+   weak linkage.
+
+
+---------------------------------------------------------------------------
+
+PORTING TO NEW ARM PLATFORMS
+
+To port Atomthreads to your ARM platform you must provide the following
+functionality in your platform folder (in all cases example filenames are
+from the qemu_integratorcp sample platform):
+
+ * Startup code: see Reset_Handler in startup.s. Typically this will be (at
+   least in the first few instructions) some assembly code, and will set up
+   the initial stack pointer, perform any copying of segments from flash to
+   RAM, zero the BSS section etc, before branching to the main application
+   function (e.g. main()). At some point during initialisation the timer
+   tick interrupt required by the OS should be started (100 ticks per
+   second) and this might be done here in the very early startup code. Note
+   that some compiler toolchains will provide a portion of the C startup
+   code e.g. the function _mainCRTStartup() provided by some GCC
+   toolchains.
+ * Interrupt vector table: see __interrupt_vector_table in startup.s.
+   Typically this will contain at least an entry for the startup/reset
+   code, and an entry for the hardware IRQ handler. In order to share
+   common code amongst all platforms, the hardware IRQ handler
+   (archIRQHandler()) is actually implemented in the common ARM port
+   folder but calls back out to a dispatcher function in your platform
+   folder to determine the source of the interrupt and handle it
+   appropriately. Your platform folder should contain this dispatcher
+   function (__interrupt_dispatcher). It must support at least the timer
+   interrupt service routine (atomTimerTick()) required by the OS. The
+   dispatcher also handles other hardware interrupt sources; it determines
+   the source of the IRQ and calls out to the appropriate ISR for that 
+   interrupt.
+ * Linker script: Here you should specify the location of the interrupt
+   vector table within RAM, location of code/text segment etc. The
+   Atomthreads ARM port does not dictate particular section names or
+   layout unless your toolchain does not provide a suitable syscalls.c and
+   you wish to use heap. In that case you will (at least initially) be
+   using the heap implementation _sbrk() in syscalls.c in the common ARM
+   port which expects "heap_top" and "end" (heap_base) to be defined by the
+   linker script. These names can be easily changed in ports/arm/syscalls.c
+   if necessary.
+ * UART driver: You should provide at least a UART write routine If you
+   would like to see debug statements, for example to see the results of
+   running the automated test suite. See uart.c for a simple example. Note
+   that for QEMU targets some semihosted toolchains will implement this for
+   you, in which case you won't need either ports/arm/syscalls.c or a UART
+   driver.
+
+
+---------------------------------------------------------------------------

ports/arm/atomport-asm.s

@@ -0,0 +1,210 @@
+/*
+  Copyright (c) 2012, Natie van Rooyen. All rights reserved.
+ 
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+ 
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+  2. Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+  3. No personal names or organizations' names associated with the
+     Atomthreads project may be used to endorse or promote products
+     derived from this software without specific prior written permission.
+ 
+  THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+
+/**/
+
+
+
+.global    archIRQHandler
+.global    contextEnterCritical
+.global    contextExitCritical
+.global    contextEnableInterrupts
+.global    archContextSwitch
+.global    archFirstThreadRestore
+
+
+.extern __interrupt_dispatcher 
+
+/**/
+.equ USR_MODE,            0x10
+.equ FIQ_MODE,            0x11
+.equ IRQ_MODE,            0x12
+.equ SVC_MODE,            0x13
+.equ ABT_MODE,            0x17
+.equ UND_MODE,            0x1B
+.equ SYS_MODE,            0x1F
+
+.equ I_BIT,               0x80        /* when I bit is set, IRQ is disabled */
+.equ F_BIT,               0x40        /* when F bit is set, FIQ is disabled */
+
+
+.text
+.code 32
+
+
+/*
+ * \b archContextSwitch
+ *
+ * Architecture-specific context switch routine.
+ *
+ * Note that interrupts are always locked out when this routine is
+ * called. For cooperative switches, the scheduler will have entered
+ * a critical region. For preemptions (called from an ISR), the
+ * ISR will have disabled interrupts on entry.
+ *
+ * @param[in] old_tcb_ptr Pointer to the thread being scheduled out
+ * @param[in] new_tcb_ptr Pointer to the thread being scheduled in
+ *
+ * @return None
+ *
+ * void archContextSwitch (ATOM_TCB *old_tcb_ptr, ATOM_TCB *new_tcb_ptr)
+ */
+archContextSwitch:
+    STMFD       sp!, {r4 - r11, lr}             /* Save registers */
+
+    STR         sp, [r0]                        /* Save old SP in old_tcb_ptr->sp_save_ptr (first TCB element) */
+    LDR         r1, [r1]                        /* Load new SP from new_tcb_ptr->sp_save_ptr (first TCB element) */
+    MOV         sp, r1                           
+
+    LDMFD       sp!, {r4 - r11, pc}             /* Load new registers */
+
+
+/**
+ * \b archFirstThreadRestore
+ *
+ * Architecture-specific function to restore and start the first thread.
+ * This is called by atomOSStart() when the OS is starting.
+ *
+ * This function will be largely similar to the latter half of
+ * archContextSwitch(). Its job is to restore the context for the
+ * first thread, and finally enable interrupts (although we actually
+ * enable interrupts in thread_shell() for new threads in this port
+ * rather than doing it explicitly here).
+ *
+ * It expects to see the context saved in the same way as if the
+ * thread has been previously scheduled out, and had its context
+ * saved. That is, archThreadContextInit() will have been called
+ * first (via atomThreadCreate()) to create a "fake" context save
+ * area, containing the relevant register-save values for a thread
+ * restore.
+ *
+ * Note that you can create more than one thread before starting
+ * the OS - only one thread is restored using this function, so
+ * all other threads are actually restored by archContextSwitch().
+ * This is another reminder that the initial context set up by
+ * archThreadContextInit() must look the same whether restored by
+ * archFirstThreadRestore() or archContextSwitch().
+ *
+ * @param[in] new_tcb_ptr Pointer to the thread being scheduled in
+ *
+ * @return None
+ *
+ * void archFirstThreadRestore (ATOM_TCB *new_tcb_ptr)
+ */
+archFirstThreadRestore:
+    LDR         r0, [r0]                        /* Get SP (sp_save_ptr is conveniently first element of TCB) */
+    MOV         sp, r0                          /* Load new stack pointer */
+    LDMFD       sp!, {r4 - r11, pc}             /* Load new registers */
+
+
+/**
+ *  \b contextEnableInterrupts
+ *
+ *  Enables interrupts on the processor
+ *
+ *  @return None
+ */
+contextEnableInterrupts:
+    MRS         r0, CPSR
+    MOV         r1, #I_BIT
+    BIC         r0, r0, r1
+    MSR         CPSR_c, r0
+    BX          lr
+
+
+/**
+ *  \b contextExitCritical
+ *
+ *  Exit critical section (restores interrupt posture)
+ *
+ *  @param[in] r0 Interrupt Posture
+ *
+ *  @return None
+ */
+contextExitCritical:
+    MSR         CPSR_cxsf, r0
+    BX          lr
+
+
+/**
+ *  \b contextEnterCritical
+ *
+ *  Enter critical section (disables interrupts)
+ *
+ *  @return Current interrupt posture
+ */
+contextEnterCritical:
+    MRS         r0, CPSR
+    ORR         r1, r0, #I_BIT
+    MSR         CPSR_cxsf, r1
+    BX          lr
+
+
+/**
+ *  \b archIRQHandler
+ *
+ *  IRQ entry point.
+ *
+ *  Save the process/thread context onto its own stack before calling __interrupt_dispatcher().
+ *  __interrupt_dispatcher() might switch stacks. On return the same context is popped from the 
+ *  stack and control is returned to the process.
+ *
+ *  @return None
+ */
+archIRQHandler:
+
+    MSR         cpsr_c, #(SVC_MODE | I_BIT)     /* Save current process context in process stack */
+    STMFD       sp!, {r0 - r3, ip, lr}          
+                                                
+    MSR         cpsr_c, #(IRQ_MODE | I_BIT)     /* Save lr_irq and spsr_irq in process stack */
+    SUB         lr, lr, #4                      
+    MOV         r1, lr                          
+    MRS         r2, spsr                        
+    MSR         cpsr_c, #(SVC_MODE | I_BIT)     
+    STMFD       sp!, {r1, r2}                   
+                                                
+    BL          __interrupt_dispatcher          /* Dispatch the interrupt to platform folder for
+                                                   the timer tick interrupt or a simular function
+                                                   for other interrupts. Some of those IRQs may
+                                                   call Atomthreads kernel routines and cause a
+                                                   thread switch. */
+
+    LDMFD       sp!, {r1, r2}                   /* Restore lr_irq and spsr_irq from process stack */
+    MSR         cpsr_c, #(IRQ_MODE | I_BIT)     
+    STMFD       sp!, {r1}                       
+    MSR         spsr_cxsf, r2                   
+                                                
+    MSR         cpsr_c, #(SVC_MODE | I_BIT)     /* Restore process regs */
+    LDMFD       sp!, {r0 - r3, ip, lr}          
+                                                
+    MSR         cpsr_c, #(IRQ_MODE | I_BIT)     /* Exit from IRQ */
+    LDMFD       sp!, {pc}^
+

ports/arm/atomport-private.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2012, Natie van Rooyen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_PORT_PRIVATE_H
+#define __ATOM_PORT_PRIVATE_H
+
+
+/* Function prototypes */
+extern void archIRQHandler (void);
+
+/* Platform-specific interrupt dispatcher called on receipt of IRQ */
+extern void __interrupt_dispatcher (void);
+
+#endif /* __ATOM_PORT_PRIVATE_H */

ports/arm/atomport-tests.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2012, Natie van Rooyen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_PORT_TESTS_H
+#define __ATOM_PORT_TESTS_H
+
+/* Include Atomthreads kernel API */
+#include "atom.h"
+
+/* Include printf for ATOMLOG() */
+#include <stdio.h>
+
+
+/* Logger macro for viewing test results */
+#define ATOMLOG     printf
+
+/*
+ * String location macro: for platforms which need to place strings in
+ * alternative locations, e.g. on avr-gcc strings can be placed in
+ * program space, saving SRAM. On most platforms this can expand to
+ * empty.
+ */
+#define _STR(x)     x
+
+/* Default thread stack size (in bytes). Allow plenty for printf(). */
+#define TEST_THREAD_STACK_SIZE      4096
+
+/* Uncomment to enable logging of stack usage to UART */
+/* #define TESTS_LOG_STACK_USAGE */
+
+
+#endif /* __ATOM_PORT_TESTS_H */
+

ports/arm/atomport.c

@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2013, Natie van Rooyen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "atom.h"
+#include "atomport.h"
+
+
+/** Functions defined in atomport_s.s */
+extern void contextEnableInterrupts (void);
+
+
+/** Forward declarations */
+static void thread_shell (void);
+
+
+/**
+ * \b thread_shell
+ *
+ * Shell routine which is used to call all thread entry points.
+ *
+ * This routine is called whenever a new thread is starting, and
+ * provides a simple wrapper around the thread entry point that
+ * allows us to carry out any actions we want to do on thread's
+ * first starting up, or returning after completion.
+ *
+ * We mainly just want to make sure interrupts are enabled when a
+ * thread is run for the first time. This can be done via stack
+ * restores when threads are first run, but it's handy to have this
+ * wrapper anyway to run some common code if threads run to
+ * completion.
+ *
+ * A thread shell is also handy for providing port users with a place
+ * to do any other initialisation that must be done for each thread
+ * (e.g. opening stdio files etc).
+ *
+ * @return None
+ */
+static void thread_shell (void)
+{
+    ATOM_TCB *curr_tcb;
+
+    /* Get the TCB of the thread being started */
+    curr_tcb = atomCurrentContext();
+
+    /**
+     * Enable interrupts - these will not be enabled when a thread
+     * is first restored.
+     */
+    contextEnableInterrupts ();
+
+    /* Call the thread entry point */
+    if (curr_tcb && curr_tcb->entry_point)
+    {
+        curr_tcb->entry_point(curr_tcb->entry_param);
+    }
+
+    /* Thread has run to completion: remove it from the ready list */
+    curr_tcb->suspended = TRUE;
+    atomSched (FALSE);
+}
+
+
+/**
+ * \b archThreadContextInit
+ *
+ * Architecture-specific thread context initialisation routine.
+ *
+ * This function must set up a thread's context ready for restoring
+ * and running the thread via archFirstThreadRestore() or
+ * archContextSwitch().
+ *
+ * The layout required to fill the correct register values is
+ * described in archContextSwitch(). Note that not all registers
+ * are restored by archContextSwitch() and archFirstThreadRestore()
+ * as this port takes advantage of the fact that not all registers
+ * must be stored by ARM gcc C subroutines. This means that we don't
+ * provide start values for those registers, as they are "don't cares".
+ *
+ * @param[in] tcb_ptr Pointer to the TCB of the thread being created
+ * @param[in] stack_top Pointer to the top of the new thread's stack
+ * @param[in] entry_point Pointer to the thread entry point function
+ * @param[in] entry_param Parameter to be passed to the thread entry point
+ *
+ * @return None
+ */
+void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param)
+{
+    uint32_t *stack_ptr;
+
+    /** Start at stack top */
+    tcb_ptr->sp_save_ptr = stack_ptr = stack_top;
+
+    /**
+     * After restoring all of the context registers, the thread restore
+     * routines will return to the address of the calling routine on the
+     * stack. In this case (the first time a thread is run) we "return"
+     * to the entry point for the thread. That is, we store the thread
+     * entry point in the place that return will look for the return
+     * address: the stack.
+     *
+     * Note that we are using the thread_shell() routine to start all
+     * threads, so we actually store the address of thread_shell()
+     * here. Other ports may store the real thread entry point here
+     * and call it directly from the thread restore routines.
+     *
+     * Because we are filling the stack from top to bottom, this goes
+     * on the stack first (at the top).
+     */
+    *stack_ptr-- = (uint32_t)thread_shell;
+
+    /**
+     * Store starting register values for R4-R11
+     */
+    *stack_ptr-- = (uint32_t) 0x00001111;   /* R11 */
+    *stack_ptr-- = (uint32_t) 0x00001010;   /* R10 */
+    *stack_ptr-- = (uint32_t) 0x00000909;   /* R9 */
+    *stack_ptr-- = (uint32_t) 0x00000808;   /* R8 */
+    *stack_ptr-- = (uint32_t) 0x00000707;   /* R7 */
+    *stack_ptr-- = (uint32_t) 0x00000606;   /* R6 */
+    *stack_ptr-- = (uint32_t) 0x00000505;   /* R5 */
+    *stack_ptr   = (uint32_t) 0x00000404;   /* R4 */
+
+    /**
+     * All thread context has now been initialised. Save the current
+     * stack pointer to the thread's TCB so it knows where to start
+     * looking when the thread is started.
+     */
+    tcb_ptr->sp_save_ptr = stack_ptr;
+
+}
+

ports/arm/atomport.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2012, Natie van Rooyen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_PORT_H
+#define __ATOM_PORT_H
+
+/* Portable uint8_t and friends available from stdint.h on this platform */
+#include <stdint.h>
+
+/* Definition of NULL is available from stddef.h on this platform */
+#include <stddef.h>
+
+/* Required number of system ticks per second (normally 100 for 10ms tick) */
+#define SYSTEM_TICKS_PER_SEC            100
+
+
+/* Size of each stack entry / stack alignment size (32 bits on this platform) */
+#define STACK_ALIGN_SIZE                sizeof(uint32_t)
+
+/**
+ * Architecture-specific types.
+ * Most of these are available from stdint.h on this platform, which is
+ * included above.
+ */
+#define POINTER void *
+
+/* *
+ *
+ * Functions defined in atomport_arm.asm
+ *
+ */
+extern uint32_t  contextEnterCritical (void) ;
+extern void      contextExitCritical (uint32_t posture) ;
+
+
+/**
+ * Critical region protection: this should disable interrupts
+ * to protect OS data structures during modification. It must
+ * allow nested calls, which means that interrupts should only
+ * be re-enabled when the outer CRITICAL_END() is reached.
+ */
+#define CRITICAL_STORE          uint32_t __atom_critical
+#define CRITICAL_START()        __atom_critical = contextEnterCritical()
+#define CRITICAL_END()          contextExitCritical(__atom_critical)
+
+/* Uncomment to enable stack-checking */
+/* #define ATOM_STACK_CHECKING */
+
+
+#endif /* __ATOM_PORT_H */

ports/arm/platforms/dm36x/Makefile

@@ -0,0 +1,150 @@
+############
+# Settings #
+############
+
+# Build all test applications:
+#   make
+#
+# Run all tests communicating via UART
+#   make tests
+
+# Location of build tools and atomthreads sources
+KERNEL_DIR=../../../../kernel
+TESTS_DIR=../../../../tests
+PORT_DIR=../..
+CC=arm-none-eabi-gcc
+OBJCOPY=arm-none-eabi-objcopy
+
+# Location of TFTP root folder for running tests via U-Boot/TFTP.
+# Note, you may need to run the Makefile as root in order to write
+# to this folder.
+TESTS_TFTPROOT=/var/lib/tftpboot
+
+# TTY device and baudrate for automated tests.
+TESTS_TTYDEV=/dev/ttyUSB0
+TESTS_TTYBAUD=115200
+
+# Enable stack-checking.
+#STACK_CHECK=true
+
+# Test programs: Log stack usage to UART (if STACK_CHECK is enabled)
+#TESTS_LOG_STACK=true
+
+# Directory for built objects
+BUILD_DIR=build
+
+# Platform-specific object files
+PLATFORM_OBJECTS = atomport-private.o uart.o
+PLATFORM_ASM_OBJECTS = startup.o
+
+# Port-specific object files
+PORT_OBJECTS = atomport.o tests-main.o syscalls.o
+PORT_ASM_OBJECTS = atomport-asm.o
+
+# Kernel object files
+KERNEL_OBJECTS = atomkernel.o atomsem.o atommutex.o atomtimer.o atomqueue.o
+
+# Collection of built objects (excluding test applications)
+ALL_OBJECTS = $(PLATFORM_OBJECTS) $(PLATFORM_ASM_OBJECTS) $(PORT_OBJECTS) $(PORT_ASM_OBJECTS) $(KERNEL_OBJECTS)
+BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS))
+
+# Test object files (dealt with separately as only one per application build)
+TEST_OBJECTS = $(notdir $(patsubst %.c,%.o,$(wildcard $(TESTS_DIR)/*.c)))
+
+# Target application filenames for each test object
+TEST_UIMAGES = $(patsubst %.o,%.uImage,$(TEST_OBJECTS))
+TEST_BINS = $(patsubst %.o,%.bin,$(TEST_OBJECTS))
+TEST_ELFS = $(patsubst %.o,%.elf,$(TEST_OBJECTS))
+
+# Search build/output directory for dependencies
+vpath %.o ./$(BUILD_DIR)
+vpath %.elf ./$(BUILD_DIR)
+
+# GCC flags
+CFLAGS=-g -c -mcpu=arm926ej-s -ffreestanding -Wall -Werror
+AFLAGS=$(CFLAGS) -x assembler-with-cpp
+LFLAGS=-mcpu=arm926ej-s -Tsystem.ld -Wall
+
+# Enable stack-checking options (disable if not required)
+ifeq ($(STACK_CHECK),true)
+CFLAGS += -DATOM_STACK_CHECKING
+endif
+ifeq ($(TESTS_LOG_STACK),true)
+CFLAGS += -DTESTS_LOG_STACK_USAGE
+endif
+
+
+#################
+# Build targets #
+#################
+
+# All tests
+all: $(BUILD_DIR) $(TEST_ELFS) $(TEST_BINS) $(TEST_UIMAGES) Makefile
+
+# Make build/output directory
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
+# Test ELF files (one application build for each test)
+$(TEST_ELFS): %.elf: %.o $(ALL_OBJECTS)
+	$(CC) $(LFLAGS) $(BUILD_DIR)/$(notdir $<) $(BUILT_OBJECTS) --output $(BUILD_DIR)/$@ -Wl,-Map,$(BUILD_DIR)/$(basename $@).map
+
+# Test BIN files (one application build for each test)
+$(TEST_BINS): %.bin: %.elf $(TEST_ELFS)
+	$(OBJCOPY) -O binary $(BUILD_DIR)/$(basename $@).elf $(BUILD_DIR)/$(basename $@).bin
+
+# Test uImage files (one application build for each test)
+$(TEST_UIMAGES): %.uImage: %.bin $(TEST_BINS)
+	gzip -9 -c $(BUILD_DIR)/$(basename $@).bin > $(BUILD_DIR)/$(basename $@).bin.gz
+	mkimage -A arm -T kernel -C gzip -a 0x80000000 -e 0x80000000 -n "Atomthreads application" -d $(BUILD_DIR)/$(basename $@).bin.gz $(BUILD_DIR)/$(basename $@).uImage
+
+# Kernel objects builder
+$(KERNEL_OBJECTS): %.o: $(KERNEL_DIR)/%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Test objects builder
+$(TEST_OBJECTS): %.o: $(TESTS_DIR)/%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Platform C objects builder
+$(PLATFORM_OBJECTS): %.o: ./%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) -I$(TESTS_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Platform asm objects builder
+$(PLATFORM_ASM_OBJECTS): %.o: ./%.s
+	$(CC) -c $(AFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Port C objects builder
+$(PORT_OBJECTS): %.o: $(PORT_DIR)/%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) -I$(TESTS_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Port asm objects builder
+$(PORT_ASM_OBJECTS): %.o: $(PORT_DIR)/%.s
+	$(CC) -c $(AFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# .lst file builder
+%.lst: %.c
+	$(CC) $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) -I$(TESTS_DIR) -Wa,-al $< > $@
+
+# Clean
+clean:
+	rm -f *.o *.elf *.map *.lst
+	rm -rf doxygen-kernel
+	rm -rf doxygen-arm
+	rm -rf doxygen-platform
+	rm -rf build
+
+# Generate Doxygen documentation
+doxygen:
+	doxygen $(KERNEL_DIR)/Doxyfile
+	doxygen ../../Doxyfile
+	doxygen ./Doxyfile
+
+# Run tests on target with expect and serial output
+phony_test_bins = $(addsuffix .sim, $(TEST_BINS))
+tests: $(phony_test_bins)
+.PHONY: tests $(phony_test_bins)
+$(phony_test_bins):
+	cp $(BUILD_DIR)/$(basename $@) $(TESTS_TFTPROOT)/test.bin
+	@echo Running test $(basename $@)
+	./run_test.exp $(TESTS_TTYDEV) $(TESTS_TTYBAUD)

ports/arm/platforms/dm36x/README

@@ -0,0 +1,213 @@
+---------------------------------------------------------------------------
+
+Library:      Atomthreads DaVinci DM365/DM368 Platform.
+Author:       Kelvin Lawson <info@atomthreads.com>
+Website:      http://atomthreads.com
+License:      BSD Revised
+
+---------------------------------------------------------------------------
+
+DaVinci DM36x (ARM926EJ-S) Platform
+
+The "dm36x" platform folder contains sources for building a sample
+Atomthreads RTOS application for DaVinci DM365 and DM368 (ARM926EJ-S)
+platforms.
+
+This has been tested on a DM368 Leopardboard platform, but will work on any
+DM36x-based platform.
+
+
+---------------------------------------------------------------------------
+
+SOURCE LAYOUT
+
+All of the cross-platform kernel code is contained in the top-level 
+'kernel' folder, while ports to specific CPU architectures are contained in
+the 'ports' folder tree. To support multiple ARM boards/platforms using a
+single common ARM architecture port, the ARM port contains 'platform'
+sub-folders in which the board/platform-specific code is situated. This
+allows the sharing of common ARM port code between many different ARM
+boards with different interrupt controllers, UARTs etc but which all reuse
+the same common core ARM context-switching code.
+
+This platform contains a few key platform-specific files:
+
+ * startup.s: Interrupt vector table and basic startup assembly code
+ * atomport-private.c: Low level initialisation for this platform
+ * uart.c: Simple UART implementation for debug purposes
+
+The common ARM architecture port that is used across all platforms contains
+the basic code for thread-switching on all ARM platforms:
+
+ * atomport.c: Those functions which can be written in C
+ * atomport-asm.s: The main register save/restore assembler routines
+
+Each Atomthreads port requires also a header file which describes various
+architecture-specific details such as appropriate types for 8-bit, 16-bit
+etc variables, the port's system tick frequency, and macros for performing
+interrupt lockouts / critical sections:
+
+ * atomport.h: Port-specific header required by the kernel for each port
+
+A couple of additional source files are also included in the common ARM port:
+
+ * tests-main.c: Main application file (used for launching automated tests)
+ * syscalls.c: Simple implementation of open/close/read/write for stdio
+
+Atomthreads includes a suite of automated tests which prove the key OS
+functionality, and can be used with any architecture ports. This platform
+provides an easy mechanism for building and quickly running the test suite
+using a serial port connected to real hardware to prove the OS.
+
+
+---------------------------------------------------------------------------
+
+GCC TOOLCHAIN
+
+The port works out-of-the-box with the GCC tools (for building). It can be
+built on any OS for which GCC is available, and was tested using the
+CodeSourcery toolchain (2009q3 non-Linux but others should be supported).
+Note that the Makefile for this platform assumes that your GCC binary is
+named "arm-none-eabi-gcc".
+
+Currently we assume that the toolchain will provide some header files like
+stdint.h. Not all toolchains will include this, in which case you simply
+need to add definitions for int32_t and friends in atomport.h, in place of
+the include declaration for stdint.h.
+
+
+---------------------------------------------------------------------------
+
+OTHER PREREQUISITES
+
+Running the entire automated test suite in one command via "make tests"
+requires the "expect" program.
+
+".bin" images bootable via U-boot are created as part of the build but if
+uImage format is preferred then the "mkimage" application is also
+required.
+
+
+---------------------------------------------------------------------------
+
+BUILDING THE SOURCE
+
+A Makefile is provided for building the kernel, port, platform and
+automated tests. Make sure the ARM GCC toolchain is in the path
+(e.g. "PATH=$PATH:/opt/arm-2009q3/bin && export path") and carry out the
+full build using the following:
+
+ * make all
+
+All objects are built into the 'build' folder under 
+ports/arm/platforms/dm36x. The build process builds separate target
+applications for each automated test, and appropriate ELF/BIN files can be
+found in the build folder ready for running on the target. Each test is
+built and run as a separate application.
+
+
+All built objects etc can be cleaned using:
+
+ * make clean
+
+
+The Atomthreads sources are documented using Doxygen markup. You can build
+both the kernel and port documentation from this folder using:
+
+ * make doxygen
+
+
+---------------------------------------------------------------------------
+
+PLATFORM SPECIFICS
+
+This RTOS port was developed on the DM368 Leopardboard, but there is
+currently very little board-specific code present, other than the choice of
+UART (the Leopardboard uses UART0 but many boards use UART1). The UART is
+used to print out pass/fail indications and other information via a serial
+debug cable connected to the board. For other boards using UART1 you may
+simply change the UART_BASE definition in uart.c.
+
+
+---------------------------------------------------------------------------
+
+AUTOMATED TESTS
+
+Atomthreads contains a set of generic kernel tests which can be run on any
+port to prove that all core functionality is working on your target.
+
+The full set of tests can be found in the top-level 'tests' folder. Each of
+these tests is built as an independent application in the 'build' folder.
+
+These can be run on the target using the instructions below.
+
+To view the test results, connect a serial debug cable to your target
+platform. On starting, the test applications print out "Go" on the UART.
+Once the test is complete they will print out "Pass" or "Fail", along with
+other information if the test failed.
+
+Most of the tests complete within a few seconds, but some (particularly
+the stress tests) can take longer, so be patient. 
+
+The full suite of tests endeavours to exercise as much of the kernel code
+as possible, and can be used for quick confirmation of core OS
+functionality if you ever need to make a change to the kernel or port.
+
+The test application main() is contained in tests-main.c. This initialises
+the OS, creates a main thread, and calls out to the test modules.
+
+
+---------------------------------------------------------------------------
+
+RUNNING THE FULL TEST SUITE
+
+It is possible to run the full automated test suite on the target board.
+This is very useful for quick verification of the entire test suite after
+making any software changes.
+
+A single command runs every single test application on the target, and
+automatically parses the UART output to verify that each test case passes.
+
+This requires the "expect" application on your development PC.
+
+To run all tests in one command, type:
+
+ * make tests
+
+This will download every single test application to your TFTP folder one at
+a time, ready for the target to load via U-Boot, and quit immediately if
+any one test fails.
+
+You should set your target board to load the file "test.bin" via TFTP and
+hit the reset button after each test has completed (when prompted).
+The U-boot "bootcmd" variable should be set as follows:
+
+ * setenv 'tftpboot 0x80000000 test.bin; go 0x80000000'
+ * saveenv
+
+Now when you run "make tests" it will copy each test application binary
+into your TFTP root folder one-by-one, and request that you reset the board
+to start the next test running. Passes or failures are reported, and the
+test suite quits if any test suite failures are encountered.
+
+The ability to run these automated tests in one command allows you to
+easily include the OS test suite in your nightly build or continous
+integration system and quickly find out if any of your local changes have
+caused any of the operating system tests to fail. In order to include them
+in a nightly test run you will need to set the test applications to
+automatically reset after running each test.
+
+
+---------------------------------------------------------------------------
+
+WRITING APPLICATIONS
+
+The easiest way to start a new application which utilises the Atomthreads
+scheduler is to base your main application startup on tests-main.c. This
+initialises the OS and calls out to the test module entry functions. You
+can generally simply replace the call to the test modules by a call to your
+own application startup code.
+
+
+---------------------------------------------------------------------------
+

ports/arm/platforms/dm36x/atomport-private.c

@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdio.h>
+#include <stdarg.h>
+#include "atomport.h"
+#include "atomport-private.h"
+#include "atom.h"
+#include "atomport.h"
+#include "dm36x-io.h"
+#include "uart.h"
+ 
+
+/** Imports required by C startup code */
+extern unsigned long _start_vectors, _end_vectors, _end_text, _start_data, _end_data, _start_bss, _end_bss;
+extern int main(void);
+
+
+/** Timer input clock speed: 24MHz */
+#define TIMER_CLK       24000000
+
+
+/** Register access macros */
+#define TIMER0_REG(offset)      *(volatile uint32_t *)(DM36X_TIMER0_BASE + offset)
+#define INTC_REG(offset)        *(volatile uint32_t *)(DM36X_INTC_BASE + offset)
+
+
+/**
+ * \b _mainCRTStartup
+ *
+ * C startup code for environments without a suitable built-in one.
+ * May be provided by the compiler toolchain in some cases.
+ *
+ */
+extern void _mainCRTStartup (void) __attribute__((weak));
+void _mainCRTStartup(void)
+{
+    unsigned long *src;
+    unsigned long *dst;
+
+    // Copy vector table from SRAM to IRAM0 (ARM vector table must be at 0x00000000)
+    src = &_start_vectors;
+    dst = (unsigned long *)0x00000000;
+    while(src < &_end_vectors)
+        *(dst++) = *(src++);
+
+#ifdef ROM
+    // Running from ROM: copy data section to RAM
+    src = &_end_text;
+    dst = &_start_data;
+    while(dst < &_end_data)
+        *(dst++) = *(src++);
+#endif
+
+    // Clear BSS
+    src = &_start_bss;
+    while(src < &_end_bss)
+        *(src++) = 0;
+
+    // Jump to main application entry point
+    main();
+}
+
+
+/**
+ * \b low_level_init
+ *
+ * Initializes the PIC and starts the system timer tick interrupt.
+ *
+ */
+int
+low_level_init (void)
+{
+    /* Initialise TIMER0 registers for interrupt 100 times per second */
+
+    /* Reset & disable all TIMER0 timers */
+    TIMER0_REG(DM36X_TIMER_INTCTL_STAT) = 0;    /* Disable interrupts */
+    TIMER0_REG(DM36X_TIMER_TCR) = 0;            /* Disable all TIMER0 timers */
+    TIMER0_REG(DM36X_TIMER_TGCR) = 0;           /* Put all TIMER0 timers in reset */
+    TIMER0_REG(DM36X_TIMER_TIM12) = 0;          /* Clear Timer 1:2 */
+
+    /* Set up Timer 1:2 in 32-bit unchained mode */
+    TIMER0_REG(DM36X_TIMER_TGCR) = (1 << 2);    /* Select 32-bit unchained mode (TIMMODE) */
+    TIMER0_REG(DM36X_TIMER_TGCR) |= (1 << 0);   /* Remove Timer 1:2 from reset (TIM12RS) */
+    TIMER0_REG(DM36X_TIMER_PRD12) = (TIMER_CLK / SYSTEM_TICKS_PER_SEC) - 1;     /* Set period to 100 ticks per second (PRD12) */
+    TIMER0_REG(DM36X_TIMER_TCR) |= (0 << 8);    /* Select external clock source for Timer 1:2 (CLKSRC12) */
+
+    /* Enable interrupts */
+    TIMER0_REG(DM36X_TIMER_INTCTL_STAT) = (1 << 1) | (1 << 0);  /* Enable/ack Compare/Match interrupt for Timer 1:2 */
+
+    /* Enable timer */
+    TIMER0_REG(DM36X_TIMER_TCR) |= (2 << 6);    /* Enable Timer 1:2 continuous (ENAMODE12) */
+
+    /* Initialise INTC interrupt controller (all at lowest priority 7) */
+    INTC_REG(DM36X_INTC_PRI0) = 0x77777777;
+    INTC_REG(DM36X_INTC_PRI1) = 0x77777777;
+    INTC_REG(DM36X_INTC_PRI2) = 0x77777777;
+    INTC_REG(DM36X_INTC_PRI3) = 0x77777777;
+    INTC_REG(DM36X_INTC_PRI4) = 0x77777777;
+    INTC_REG(DM36X_INTC_PRI5) = 0x77777777;
+    INTC_REG(DM36X_INTC_PRI6) = 0x77777777;
+    INTC_REG(DM36X_INTC_PRI7) = 0x77777777;
+    INTC_REG(DM36X_INTC_INTCTL) = 0;
+    INTC_REG(DM36X_INTC_EABASE) = 0;
+    INTC_REG(DM36X_INTC_EINT0) = 0;
+    INTC_REG(DM36X_INTC_EINT1) = 0;
+
+    /* Ack TINT0 IRQ in INTC interrupt controller */
+    INTC_REG(DM36X_INTC_IRQ1) = (1 << (DM36X_INTC_VEC_TINT0 - 32));
+
+    /* Enable TINT0 IRQ in INTC interrupt controller */
+    INTC_REG(DM36X_INTC_EINT1) |= (1 << (DM36X_INTC_VEC_TINT0 - 32));
+
+    return 0 ;
+}
+
+
+/**
+ * \b __interrupt_dispatcher
+ *
+ * Interrupt dispatcher: determines the source of the IRQ and calls
+ * the appropriate ISR.
+ *
+ * Currently only the OS system tick ISR is implemented.
+ *
+ * Note that any ISRs which call Atomthreads OS routines that can
+ * cause rescheduling of threads must be surrounded by calls to
+ * atomIntEnter() and atomIntExit().
+ *
+ */
+void
+__interrupt_dispatcher (void) 
+{
+    uint32_t vector;
+    uint32_t irqentry;
+
+    /* Read IRQENTRY register to determine the source of the interrupt */
+    irqentry = INTC_REG(DM36X_INTC_IRQENTRY);
+
+    /* Check for spurious interrupt */
+    if (irqentry == 0)
+    {
+        /* Spurious interrupt */
+        uart_write_halt ("Spurious IRQ\n");
+	}
+	else
+	{
+        /* Translate from vector address to vector number */
+        vector = (INTC_REG(DM36X_INTC_IRQENTRY) / 4) - 1;
+
+        /* TIMER0:12 tick interrupt (call Atomthreads timer tick ISR) */
+        if (vector == DM36X_INTC_VEC_TINT0)
+        {
+            /* Ack the interrupt immediately, could get scheduled out below */
+            INTC_REG(((vector >= 32) ? DM36X_INTC_IRQ1 : DM36X_INTC_IRQ0)) = (1 << ((vector >= 32) ? (vector - 32) : vector));
+
+            /*
+             * Let the Atomthreads kernel know we're about to enter an OS-aware
+             * interrupt handler which could cause scheduling of threads.
+             */
+            atomIntEnter();
+
+            /* Call the OS system tick handler */
+            atomTimerTick();
+
+            /* Call the interrupt exit routine */
+            atomIntExit(TRUE);
+        }
+        else
+        {
+            /* Unexpected vector */
+            uart_write_halt ("Unexpected IRQ vector\n");
+        }
+
+	}
+
+}
+
+
+/**
+ * \b null_handler
+ *
+ * Handler to catch interrupts at uninitialised vectors.
+ *
+ */
+void null_handler (void) 
+{
+    uart_write_halt ("Unhandled interrupt\n");
+}
+

ports/arm/platforms/dm36x/dm36x-io.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DM36X_IO_H__
+#define __DM36X_IO_H__
+
+#include "atomport.h"
+
+
+/*
+ * IO Addresses for use with DM36x
+ */
+
+#define DM36X_TIMER0_BASE       0x01C21400 /* TIMER0 */
+#define DM36X_TIMER_PID12       0x00
+#define DM36X_TIMER_EMUMGT      0x04
+#define DM36X_TIMER_TIM12       0x10
+#define DM36X_TIMER_TIM34       0x14
+#define DM36X_TIMER_PRD12       0x18
+#define DM36X_TIMER_PRD34       0x1C
+#define DM36X_TIMER_TCR         0x20
+#define DM36X_TIMER_TGCR        0x24
+#define DM36X_TIMER_WDTCR       0x28
+#define DM36X_TIMER_REL12       0x34
+#define DM36X_TIMER_REL34       0x38
+#define DM36X_TIMER_CAP12       0x3C
+#define DM36X_TIMER_CAP34       0x40
+#define DM36X_TIMER_INTCTL_STAT 0x44
+
+#define DM36X_INTC_BASE         0x01C48000 /* Interrupt controller */
+#define DM36X_INTC_IRQ0         0x08
+#define DM36X_INTC_IRQ1         0x0C
+#define DM36X_INTC_FIQENTRY     0x10
+#define DM36X_INTC_IRQENTRY     0x14
+#define DM36X_INTC_EINT0        0x18
+#define DM36X_INTC_EINT1        0x1C
+#define DM36X_INTC_INTCTL       0x20
+#define DM36X_INTC_EABASE       0x24
+#define DM36X_INTC_PRI0         0x30
+#define DM36X_INTC_PRI1         0x34
+#define DM36X_INTC_PRI2         0x38
+#define DM36X_INTC_PRI3         0x3C
+#define DM36X_INTC_PRI4         0x40
+#define DM36X_INTC_PRI5         0x44
+#define DM36X_INTC_PRI6         0x48
+#define DM36X_INTC_PRI7         0x4C
+#define DM36X_INTC_VEC_TINT0    32
+
+#define DM36X_UART0_BASE        0x01C20000 /* UART0 */
+#define DM36X_UART1_BASE        0x01D06000 /* UART1 */
+
+
+
+/* Function prototypes */
+extern int              low_level_init (void) ;
+
+
+#endif /* __DM36X_IO_H__ */

ports/arm/platforms/dm36x/run_test.exp

@@ -0,0 +1,50 @@
+#!/usr/bin/env expect
+
+# Expect script to check an automated test's results via a serial port
+# and check for successful completion.
+#
+# You are expected to set the target's U-boot up to automatically load
+# the app on your TFTP server called "test.bin". Before this script is
+# started the Makefile should have copied the next test binary to the
+# file "test.bin" in your TFTP root folder. The user must sit and
+# hit the reset button after every test completion in order to make
+# the board load and run the next test.bin file.
+#
+# Arguments: <serial_port_device> <baudrate> <test_bin_file>
+#
+# Returns 0 on successful test run, 1 on failure
+
+# Set the serial port baudrate
+stty [lindex $argv 1] < [lindex $argv 0]
+
+# Start the test
+spawn cat [lindex $argv 0]
+puts "Ready: reset the target!"
+
+# Expect to see the test starting within 60 seconds (give long enough
+# for user to reset the board after running the last test).
+set timeout 60
+
+# Wait for the test to start ("Go")
+expect {
+	"Go\r" {
+		puts "Test started"
+
+		# The test could take up to 3 minutes to complete once started
+		set timeout 180
+
+		# Now expect to see "Pass" or "Fail" within 3 minutes
+		expect {
+			"Pass\r" { puts "Test passed"; exit 0 }
+			"Fail\r" { puts "Test failed"; exit 1 }
+			timeout { puts "Test timed out without completing"; exit 1 }
+		}
+	}
+
+	timeout {
+		# Didn't receive "Go" within 10 seconds
+		puts "Test failed to start ('Go' not seen)"
+		exit 1
+	}
+}
+

ports/arm/platforms/dm36x/startup.s

@@ -0,0 +1,47 @@
+.section .vectors, "x"
+
+.global __interrupt_vector_table
+.extern __irq_stack_top__
+.extern __fiq_stack_top__
+.extern __svc_stack_top__
+
+
+.equ USR_MODE,            0x10
+.equ FIQ_MODE,            0x11
+.equ IRQ_MODE,            0x12
+.equ SVC_MODE,            0x13
+.equ ABT_MODE,            0x17
+.equ UND_MODE,            0x1B
+.equ SYS_MODE,            0x1F
+
+.equ I_BIT,               0x80            /* when I bit is set, IRQ is disabled */
+.equ F_BIT,               0x40            /* when F bit is set, FIQ is disabled */
+
+
+__interrupt_vector_table:
+
+  B Reset_Handler /* Reset */
+  ldr PC,=null_handler  /* Undefined */
+  ldr PC,=null_handler  /* SWI */
+  ldr PC,=null_handler  /* Prefetch Abort */
+  ldr PC,=null_handler  /* Data Abort */
+  ldr PC,=null_handler  /* reserved */
+  ldr PC,=archIRQHandler/* IRQ */
+  ldr PC,=null_handler  /* FIQ */
+ 
+
+Reset_Handler:
+
+    MSR CPSR_c,#(IRQ_MODE | I_BIT | F_BIT)
+    LDR sp,=__irq_stack_top__ /* set the IRQ stack pointer */
+    MSR CPSR_c,#(FIQ_MODE | I_BIT | F_BIT)
+    LDR sp,=__fiq_stack_top__ /* set the FIQ stack pointer */
+    MSR CPSR_c,#(SVC_MODE | I_BIT | F_BIT)
+    LDR sp,=__svc_stack_top__ /* set the SVC stack pointer */
+
+    BL low_level_init
+    BL _mainCRTStartup
+
+
+  B .
+

ports/arm/platforms/dm36x/system.ld

@@ -0,0 +1,87 @@
+
+ENTRY(__interrupt_vector_table)
+
+
+MEMORY
+{
+    sram (rwx) : ORIGIN = 0x80000000, LENGTH = 0x10000000
+}
+
+
+EXTERN(__interrupt_vector_table);
+
+
+C_STACK_SIZE = 4096;
+IRQ_STACK_SIZE = 4096;
+FIQ_STACK_SIZE = 2048;
+SVC_STACK_SIZE = 4096;
+ABT_STACK_SIZE = 2048;
+UND_STACK_SIZE = 2048;
+
+SECTIONS
+{
+
+    
+    .text :
+    {
+        _start_vectors = .;
+        *(.vectors)
+        _end_vectors = .;
+        /* Startup assembly */
+        *(.startup)
+        *(.init)
+
+        /* Rest of the code (C) */
+        *(.text)
+        *(.rodata)
+        *(.rodata*)
+
+        _end_text = .;
+
+        _start_data = .;
+        *(.data)
+        _end_data = .;
+    } >sram
+
+    .bss :
+    {
+        _start_bss = .;
+        __bss_start__ = . ;
+        *(.bss)
+    } >sram
+
+    . = ALIGN(4);
+    _end_bss = .;
+    __bss_end__ = . ;
+
+    . = ALIGN(256);
+    
+    .stack : {
+    __stack_start__ = . ;
+    . += IRQ_STACK_SIZE;
+    . = ALIGN (4);
+    __irq_stack_top__ = . ;
+    . += FIQ_STACK_SIZE;
+    . = ALIGN (4);
+    __fiq_stack_top__ = . ;
+    . += SVC_STACK_SIZE;
+    . = ALIGN (4);
+    __svc_stack_top__ = . ;
+    . += ABT_STACK_SIZE;
+    . = ALIGN (4);
+    __abt_stack_top__ = . ;
+    . += UND_STACK_SIZE;
+    . = ALIGN (4);
+    __und_stack_top__ = . ;
+    . += C_STACK_SIZE;
+    . = ALIGN (4);
+    __c_stack_top__ = . ;
+    __stack_end__ = .;
+    } >sram 
+
+}
+__end__ = .;
+_end = .;
+PROVIDE(end = .);
+
+heap_top = ORIGIN(sram) + LENGTH(sram) - 4;

ports/arm/platforms/dm36x/uart.c

@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/** 
+ * \file
+ * Simple polled UART implementation for non-hosted compiler toolchains.
+ *
+ *
+ * This is only required for non-hosted toolchains which don't implement
+ * stdout automatically for use within QEMU.
+ */
+
+#include "atom.h"
+#include "atommutex.h"
+#include "atomport.h"
+#include "dm36x-io.h"
+#include "uart.h"
+
+
+/* Constants */
+
+/** Select relevant UART for this platform */
+#define UART_BASE       DM36X_UART0_BASE
+
+/** FR Register bits */
+#define UART_FR_RXFE     0x10
+#define UART_LSR_TEMT    0x40
+
+/** UART register access macros */
+#define UART_DR(baseaddr) (*(unsigned int *)(baseaddr))
+#define UART_LSR(baseaddr) (*(((unsigned int *)(baseaddr))+0x14))
+
+
+/* Local data */
+
+/*
+ * Semaphore for single-threaded access to UART device
+ */
+static ATOM_MUTEX uart_mutex;
+
+/*
+ * Initialised flag
+ */
+static int initialised = FALSE;
+
+
+/* Forward declarations */
+static int uart_init (void);
+static void uart_write_char (const char c);
+
+
+/**
+ * \b uart_init
+ *
+ * Initialisation of UART driver. Creates a mutex that enforces
+ * single-threaded access to the UART. We poll register bits
+ * to check when space is available, which would not otherwise
+ * be thread-safe.
+ *
+ * @retval ATOM_OK Success
+ * @retval ATOM_ERROR Failed to create mutex
+ */
+static int uart_init (void)
+{
+    int status;
+
+    /* Check we are not already initialised */
+    if (initialised == FALSE)
+    {
+        /* Create a mutex for single-threaded UART access */
+        if (atomMutexCreate (&uart_mutex) != ATOM_OK)
+        {
+            /* Mutex creation failed */
+            status = ATOM_ERROR;
+        }
+        else
+        {
+            /* Success */
+            initialised = TRUE;
+            status = ATOM_OK;
+        }
+    }
+
+    /* Finished */
+    return (status);
+}
+
+
+/**
+ * \b uart_read
+ *
+ * Simple polled UART read.
+ *
+ * @param[in] ptr Pointer to receive buffer
+ * @param[in] len Max bytes to read
+ *
+ * @retval Number of bytes read
+ *
+ */
+int uart_read (char *ptr, int len)
+{
+    int todo = 0;
+
+    /* Check we are initialised */
+    if (initialised == FALSE)
+    {
+        uart_init();
+    }
+
+    /* Check parameters */
+    if ((ptr == NULL) || (len == 0))
+    {
+        return 0;
+    }
+
+    /* Block thread on private access to the UART */
+    if (atomOSStarted && atomMutexGet(&uart_mutex, 0) == ATOM_OK)
+    {
+#if 0
+        /* Wait for not-empty */
+        while(UART_FR(UART_BASE) & UART_FR_RXFE)
+            ;
+
+        /* Read first byte */
+        *ptr++ = UART_DR(UART_BASE);
+
+        /* Loop over remaining bytes until empty */
+        for (todo = 1; todo < len; todo++)
+        {
+            /* Quit if receive FIFO empty */
+            if(UART_FR(UART_BASE) & UART_FR_RXFE)
+            {
+                break;
+            }
+
+            /* Read next byte */
+            *ptr++ = UART_DR(UART_BASE);
+        }
+#endif
+
+        /* Return mutex access */
+        if (atomOSStarted)
+        {
+            atomMutexPut(&uart_mutex);
+        }
+    }
+
+    /* Return number of bytes read */
+    return todo;
+}
+
+
+/**
+ * \b uart_write
+ *
+ * Simple polled UART write.
+ *
+ * @param[in] ptr Pointer to write buffer
+ * @param[in] len Number of bytes to write
+ *
+ * @retval Number of bytes written
+ */
+int uart_write (const char *ptr, int len)
+{
+    int todo;
+
+    /* Check we are initialised */
+    if (initialised == FALSE)
+    {
+        uart_init();
+    }
+
+    /* Check parameters */
+    if ((ptr == NULL) || (len == 0))
+    {
+        return 0;
+    }
+
+    /* Block thread on private access to the UART */
+    if (atomOSStarted && atomMutexGet(&uart_mutex, 0) == ATOM_OK)
+    {
+        /* Loop through all bytes to write */
+        for (todo = 0; todo < len; todo++)
+        {
+            /* Convert \n to \r\n */
+            if (*ptr == '\n')
+                uart_write_char('\r');
+
+            /* Write byte to UART */
+            uart_write_char(*ptr++);
+        }
+
+        /* Return mutex access */
+        if (atomOSStarted)
+        {
+            atomMutexPut(&uart_mutex);
+        }
+    }
+
+    /* Return bytes-written count */
+    return len;
+}
+
+
+/**
+ * \b uart_write_halt
+ *
+ * Simple polled UART write for handling critical failures
+ * by printing out a message on the UART and looping forever.
+ * Can be called from interrupt (unlike the standard
+ * uart_write()) but is not thread-safe because it cannot
+ * take the thread-safety mutex, and hence is only useful for
+ * a last-resort catastrophic debug message.
+ *
+ * @param[in] ptr Pointer to write string
+ */
+void uart_write_halt (const char *ptr)
+{
+    /* Check parameters */
+    if (ptr != NULL)
+    {
+        /* Loop through all bytes until NULL terminator encountered */
+        while (*ptr != '\0')
+        {
+            /* Convert \n to \r\n */
+            if (*ptr == '\n')
+                uart_write_char('\r');
+
+            /* Write byte to UART */
+            uart_write_char(*ptr++);
+        }
+    }
+
+    /* Loop forever */
+    while (1)
+        ;
+
+}
+
+
+/**
+ * \b uart_putchar
+ *
+ * Simple polled UART write char.
+ *
+ * Assumes that the mutex has already been taken, or
+ * is not expected to be taken (e.g. on interrupt).
+ *
+ * @param[in] c Char to write
+ */
+static void uart_write_char (const char c)
+{
+    /* Wait for empty */
+    while(UART_LSR(UART_BASE) & UART_LSR_TEMT)
+        ;
+
+    /* Write byte to UART */
+    UART_DR(UART_BASE) = c;
+}

ports/arm/platforms/dm36x/uart.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_UART_H
+#define __ATOM_UART_H
+
+/* UART driver APIs */
+extern int uart_read (char *ptr, int len);
+extern int uart_write (const char *ptr, int len);
+extern void uart_write_halt (const char *ptr);
+
+#endif /* __ATOM_UART_H */

ports/arm/platforms/qemu_integratorcp/Makefile

@@ -0,0 +1,129 @@
+############
+# Settings #
+############
+
+# Build all test applications:
+#   make
+#
+# Run all tests within QEMU
+#   make qemutests
+
+# Location of build tools and atomthreads sources
+KERNEL_DIR=../../../../kernel
+TESTS_DIR=../../../../tests
+PORT_DIR=../..
+CC=arm-none-eabi-gcc
+OBJCOPY=arm-none-eabi-objcopy
+QEMU=qemu-system-arm
+
+# Enable stack-checking.
+#STACK_CHECK=true
+
+# Test programs: Log stack usage to UART (if STACK_CHECK is enabled)
+#TESTS_LOG_STACK=true
+
+# Directory for built objects
+BUILD_DIR=build
+
+# Platform-specific object files
+PLATFORM_OBJECTS = modules.o uart.o
+PLATFORM_ASM_OBJECTS = startup.o
+
+# Port-specific object files
+PORT_OBJECTS = atomport.o tests-main.o syscalls.o
+PORT_ASM_OBJECTS = atomport-asm.o
+
+# Kernel object files
+KERNEL_OBJECTS = atomkernel.o atomsem.o atommutex.o atomtimer.o atomqueue.o
+
+# Collection of built objects (excluding test applications)
+ALL_OBJECTS = $(PLATFORM_OBJECTS) $(PLATFORM_ASM_OBJECTS) $(PORT_OBJECTS) $(PORT_ASM_OBJECTS) $(KERNEL_OBJECTS)
+BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS))
+
+# Test object files (dealt with separately as only one per application build)
+TEST_OBJECTS = $(notdir $(patsubst %.c,%.o,$(wildcard $(TESTS_DIR)/*.c)))
+
+# Target application filenames for each test object
+TEST_ELFS = $(patsubst %.o,%.elf,$(TEST_OBJECTS))
+
+# Search build/output directory for dependencies
+vpath %.o ./$(BUILD_DIR)
+vpath %.elf ./$(BUILD_DIR)
+
+# GCC flags
+CFLAGS=-g -c -mcpu=arm926ej-s -ffreestanding -Wall -Werror
+AFLAGS=$(CFLAGS) -x assembler-with-cpp
+LFLAGS=-mcpu=arm926ej-s -Tsystem.ld -Wall
+
+# Enable stack-checking options (disable if not required)
+ifeq ($(STACK_CHECK),true)
+CFLAGS += -DATOM_STACK_CHECKING
+endif
+ifeq ($(TESTS_LOG_STACK),true)
+CFLAGS += -DTESTS_LOG_STACK_USAGE
+endif
+
+
+#################
+# Build targets #
+#################
+
+# All tests
+all: $(BUILD_DIR) $(TEST_ELFS) Makefile
+
+# Make build/output directory
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
+# Test ELF files (one application build for each test)
+$(TEST_ELFS): %.elf: %.o $(ALL_OBJECTS)
+	$(CC) $(LFLAGS) $(BUILD_DIR)/$(notdir $<) $(BUILT_OBJECTS) --output $(BUILD_DIR)/$@ -Wl,-Map,$(BUILD_DIR)/$(basename $@).map
+
+# Kernel objects builder
+$(KERNEL_OBJECTS): %.o: $(KERNEL_DIR)/%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Test objects builder
+$(TEST_OBJECTS): %.o: $(TESTS_DIR)/%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Platform C objects builder
+$(PLATFORM_OBJECTS): %.o: ./%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) -I$(TESTS_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Platform asm objects builder
+$(PLATFORM_ASM_OBJECTS): %.o: ./%.s
+	$(CC) -c $(AFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Port C objects builder
+$(PORT_OBJECTS): %.o: $(PORT_DIR)/%.c
+	$(CC) -c $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) -I$(TESTS_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Port asm objects builder
+$(PORT_ASM_OBJECTS): %.o: $(PORT_DIR)/%.s
+	$(CC) -c $(AFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# .lst file builder
+%.lst: %.c
+	$(CC) $(CFLAGS) -I. -I$(PORT_DIR) -I$(KERNEL_DIR) -I$(TESTS_DIR) -Wa,-al $< > $@
+
+# Clean
+clean:
+	rm -f *.o *.elf *.map *.lst
+	rm -rf doxygen-kernel
+	rm -rf doxygen-arm
+	rm -rf doxygen-platform
+	rm -rf build
+
+# Generate Doxygen documentation
+doxygen:
+	doxygen $(KERNEL_DIR)/Doxyfile
+	doxygen ../../Doxyfile
+	doxygen ./Doxyfile
+
+# Run tests within simavr simulator
+phony_qemu_elfs = $(addsuffix .sim, $(TEST_ELFS))
+qemutests: $(phony_qemu_elfs)
+.PHONY: qemutests $(phony_qemu_elfs)
+$(phony_qemu_elfs):
+	./run_test.exp $(QEMU) $(BUILD_DIR)/$(basename $@)

ports/arm/platforms/qemu_integratorcp/README

@@ -0,0 +1,228 @@
+---------------------------------------------------------------------------
+
+Library:      Atomthreads QEMU ARM Integrator/CP (ARM926EJ-S) Platform.
+Author:       Natie van Rooyen <natie@navaro.nl>
+Website:      http://atomthreads.com
+License:      BSD Revised
+
+---------------------------------------------------------------------------
+
+QEMU ARM Integrator/CP (ARM926EJ-S) Platform
+
+The "qemu_integratorcp" platform folder contains sources for building a
+sample Atomthreads application for the ARM Integrator/CP (ARM926EJ-S)
+platform running under QEMU.
+
+
+---------------------------------------------------------------------------
+
+SOURCE LAYOUT
+
+All of the cross-platform kernel code is contained in the top-level 
+'kernel' folder, while ports to specific CPU architectures are contained in
+the 'ports' folder tree. To support multiple ARM boards/platforms using a
+single common ARM architecture port, the ARM port contains 'platform'
+sub-folders in which the board/platform-specific code is situated. This
+allows the sharing of common ARM port code between many different ARM
+boards with different interrupt controllers, UARTs etc but which all reuse
+the same common core ARM context-switching code.
+
+This platform contains a few key platform-specific files:
+
+ * startup.s: Interrupt vector table and basic startup assembly code
+ * modules.c: Low level initialisation for this platform
+ * uart.c: Simple UART implementation for debug purposes
+
+The common ARM architecture port that is used across all platforms contains
+the basic code for thread-switching on all ARM platforms:
+
+ * atomport.c: Those functions which can be written in C
+ * atomport-asm.s: The main register save/restore assembler routines
+
+Each Atomthreads port requires also a header file which describes various
+architecture-specific details such as appropriate types for 8-bit, 16-bit
+etc variables, the port's system tick frequency, and macros for performing
+interrupt lockouts / critical sections:
+
+ * atomport.h: Port-specific header required by the kernel for each port
+
+A couple of additional source files are also included in the common ARM port:
+
+ * tests-main.c: Main application file (used for launching automated tests)
+ * syscalls.c: Simple implementation of open/close/read/write for stdio
+
+Atomthreads includes a suite of automated tests which prove the key OS
+functionality, and can be used with any architecture ports. This port
+provides an easy mechanism for building and quickly running the test suite
+using QEMU to prove the OS without requiring any target hardware.
+
+This platform folder has been tested on a variety of GCC ARM toolchains,
+including hosted and non-hosted.
+
+
+---------------------------------------------------------------------------
+
+GCC TOOLCHAIN
+
+The port works out-of-the-box with the GCC tools (for building) and QEMU 
+(for simulation). It can be built on any OS for which GCC is available, and
+was tested using the CodeSourcery toolchain (2009q3 non-Linux but others
+should be supported) and self-built toolchains such as hosted toolchains
+built by build_arm_toolchain.sh (see http://navaro.nl for details). Note
+that the Makefile for this platform assumes that your GCC binary is named
+"arm-none-eabi-gcc".
+
+Currently we assume that the toolchain will provide some header files like
+stdint.h. Not all toolchains will include this, in which case you simply
+need to add definitions for int32_t and friends in atomport.h, in place of
+the include declaration for stdint.h.
+
+Some toolchains provide newlib syscalls.c which implement stdio
+functionality via open, close, read, write. Hosted toolchains will
+automatically provide versions of these which work with QEMU, and no UART
+driver will be needed to view the stdio printf()s etc. If these are not
+provided by by the compiler toolchain then backup implementations are
+implemented within the common ARM port folder (see ports/arm/syscalls.c)
+and a UART driver is implemented here in uart.c.
+
+Similarly some toolchains provide startup assembly code via
+_mainCRTStartup(). If this is not provided by the toolchain then a backup
+version is used within modules.c.
+
+
+---------------------------------------------------------------------------
+
+OTHER PREREQUISITES
+
+QEMU is used for simulation of the target and versions 0.14.1, 1.2.0 &
+1.4.0 were tested.
+
+Running the entire automated test suite in one command via "make qemutests"
+also requires the "expect" program.
+
+
+---------------------------------------------------------------------------
+
+BUILDING THE SOURCE
+
+A Makefile is provided for building the kernel, port, platform and
+automated tests. Make sure the ARM GCC toolchain is in the path
+(e.g. "PATH=$PATH:/opt/arm-2009q3/bin && export path") as well as QEMU and
+carry out the full build using the following:
+
+ * make all
+
+All objects are built into the 'build' folder under 
+ports/arm/platforms/qemu_integrator_cp. The build process builds separate
+target applications for each automated test, and appropriate ELF files can
+be found in the build folder ready for running on the target or within
+QEMU. Each test is built and run as a separate application.
+
+
+All built objects etc can be cleaned using:
+
+ * make clean
+
+
+The Atomthreads sources are documented using Doxygen markup. You can build
+both the kernel and port documentation from this folder using:
+
+ * make doxygen
+
+
+---------------------------------------------------------------------------
+
+Integrator/CP SPECIFICS
+
+The test applications make use of the Integrator's UART to print out
+pass/fail indications and other information. For this you should connect a
+serial debug cable to the board or when running in QEMU you will see the
+UART messages on the console when running the test applications.
+
+
+---------------------------------------------------------------------------
+
+AUTOMATED TESTS
+
+Atomthreads contains a set of generic kernel tests which can be run on any
+port to prove that all core functionality is working on your target.
+
+The full set of tests can be found in the top-level 'tests' folder. Each of
+these tests is built as an independent application in the 'build' folder.
+
+These can be run on the target or within QEMU using the instructions below.
+
+To view the test results, connect a serial debug cable to your target
+platform or view the console if using QEMU. On starting, the test
+applications print out "Go" on the UART. Once the test is complete they
+will print out "Pass" or "Fail", along with other information if the test
+failed.
+
+Most of the tests complete within a few seconds, but some (particularly
+the stress tests) can take longer, so be patient. 
+
+The full suite of tests endeavours to exercise as much of the kernel code
+as possible, and can be used for quick confirmation of core OS
+functionality if you ever need to make a change to the kernel or port.
+
+The test application main() is contained in tests-main.c. This initialises
+the OS, creates a main thread, and calls out to the test modules.
+
+
+---------------------------------------------------------------------------
+
+RUNNING TESTS WITHIN THE QEMU SIMULATOR
+
+It is possible to run the full automated test suite in a simulator without
+programming the test applications into real hardware. This is very useful
+for quick verification of the entire test suite after making any software
+changes, and is much faster than downloading each test application to a
+real target.
+
+A single command runs every single test application, and automatically
+parses the (simulated) UART output to verify that each test case passes.
+
+This requires two applications on your development PC: expect and QEMU.
+
+To run all tests in one command, type:
+
+ * make qemutests
+
+This will run every single test application within the simulator and quit
+immediately if any one test fails.
+
+The ability to run these automated tests in one command (and without real
+hardware) allows you to easily include the OS test suite in your nightly
+build or continous integration system and quickly find out if any of your
+local changes have caused any of the operating system tests to fail.
+
+
+---------------------------------------------------------------------------
+
+DEBUGGING WITH QEMU
+
+You may also use QEMU in combination with GDB to debug your built
+applications. To do this you should start QEMU with "-S -s" options e.g.:
+
+ * qemu-system-arm -M integratorcp -semihosting -nographic -kernel app.elf
+
+You can now start GDB and attach to the target:
+
+ * arm-none-eabi-gdb
+ * file app.elf
+ * target remote localhost:1234
+
+
+---------------------------------------------------------------------------
+
+WRITING APPLICATIONS
+
+The easiest way to start a new application which utilises the Atomthreads
+scheduler is to base your main application startup on tests-main.c. This
+initialises the OS and calls out to the test module entry functions. You
+can generally simply replace the call to the test modules by a call to your
+own application startup code.
+
+
+---------------------------------------------------------------------------
+

ports/arm/platforms/qemu_integratorcp/modules.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2012, Natie van Rooyen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "modules.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "atomport.h"
+#include "atomport-private.h"
+#include "atom.h"
+#include "atomport.h"
+#include "uart.h"
+ 
+
+/** Imports required by C startup code */
+extern unsigned long _end_text, _start_data, _end_data, _start_bss, _end_bss;
+extern int main(void);
+
+/** Board-specific registers */
+ICP_TIMER_T * const board_timer_0 = (ICP_TIMER_T*)BOARD_BASE_ADDRESS_TIMER_0;
+ICP_PIC_T *   const board_pic     = (ICP_PIC_T*)BOARD_BASE_ADDRESS_PIC;
+
+/** TIMER0 clock speed (Hz) */
+#define TIMER0_CLOCK_SPEED     40000000
+
+
+/**
+ * \b _mainCRTStartup
+ *
+ * C startup code for environments without a suitable built-in one.
+ * May be provided by the compiler toolchain in some cases.
+ *
+ */
+extern void _mainCRTStartup (void) __attribute__((weak));
+void _mainCRTStartup(void)
+{
+    unsigned long *src;
+#ifdef ROM
+    unsigned long *dst;
+#endif
+
+#ifdef ROM
+    // Running from ROM: copy data section to RAM
+    src = &_end_text;
+    dst = &_start_data;
+    while(dst < &_end_data)
+        *(dst++) = *(src++);
+#endif
+
+    // Clear BSS
+    src = &_start_bss;
+    while(src < &_end_bss)
+        *(src++) = 0;
+
+    // Jump to main application entry point
+    main();
+}
+
+
+/**
+ * \b low_level_init
+ *
+ * Initializes the PIC and starts the system timer tick interrupt.
+ *
+ */
+int
+low_level_init (void)
+{
+
+    board_pic->IRQ_ENABLECLR = ICP_PIC_IRQ_TIMERINT0 ;
+    board_timer_0->INTCLR = 1 ;
+    board_pic->IRQ_ENABLESET |= ICP_PIC_IRQ_TIMERINT0 ;
+
+    /* Set the timer to go off 100 times per second (input clock speed is 40MHz) */
+    board_timer_0->LOAD = TIMER0_CLOCK_SPEED / SYSTEM_TICKS_PER_SEC ;
+    board_timer_0->BGLOAD = TIMER0_CLOCK_SPEED / SYSTEM_TICKS_PER_SEC ;
+    board_timer_0->CONTROL = ICP_TIMER_CONTROL_ENABLE |
+                            ICP_TIMER_CONTROL_MODE |
+                            ICP_TIMER_CONTROL_IE |
+                            ICP_TIMER_CONTROL_TIMER_SIZE ;
+
+    return 0 ;
+}
+
+
+/**
+ * \b __interrupt_dispatcher
+ *
+ * Interrupt dispatcher: determines the source of the IRQ and calls
+ * the appropriate ISR.
+ *
+ * Currently only the OS system tick ISR is implemented.
+ *
+ * Note that any ISRs which call Atomthreads OS routines that can
+ * cause rescheduling of threads must be surrounded by calls to
+ * atomIntEnter() and atomIntExit().
+ *
+ */
+void
+__interrupt_dispatcher (void) 
+{
+    unsigned int status;
+
+    /* Read STATUS register to determine the source of the interrupt */
+    status = board_pic->IRQ_STATUS;
+
+    /* Timer tick interrupt (call Atomthreads timer tick ISR) */
+    if (status | ICP_PIC_IRQ_TIMERINT0)
+    {
+        /*
+         * Let the Atomthreads kernel know we're about to enter an OS-aware
+         * interrupt handler which could cause scheduling of threads.
+         */
+        atomIntEnter();
+
+        /* Call the OS system tick handler */
+        atomTimerTick();
+
+        /* Ack the interrupt */
+        board_timer_0->INTCLR = 0x1;
+
+        /* Call the interrupt exit routine */
+        atomIntExit(TRUE);
+    }
+
+}
+
+
+/**
+ * \b null_handler
+ *
+ * Handler to catch interrupts at uninitialised vectors.
+ *
+ */
+void null_handler (void) 
+{
+    uart_write_halt ("Unhandled interrupt\n");
+}
+

ports/arm/platforms/qemu_integratorcp/modules.h

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2012, Natie van Rooyen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __MODULES_H__
+#define __MODULES_H__
+
+/*
+ *  Module definitions to use with the ARM Integrator/CP (ARM926EJ-S)
+ */
+
+#include "atomport.h"
+
+
+/* IO definitions (access restrictions to peripheral registers) */
+#define     __I     volatile           /*!< defines 'read only' permissions                 */
+#define     __O     volatile           /*!< defines 'write only' permissions                */
+#define     __IO    volatile           /*!< defines 'read / write' permissions              */
+
+
+// *****************************************************************************
+// INTEGRATORCP TIMER
+// *****************************************************************************
+typedef struct ICP_TIMER_S {
+                                                    // offset  read/write   word size  reset           Description
+        __IO uint32_t       LOAD      ;                 // 0x0000  Read/write   32         0x00000000      Load value for Timer
+        __I  uint32_t       VALUE     ;                 // 0x0004  Read         32         0xFFFFFFFF      The current value for Timer
+        __IO uint8_t        CONTROL   ;                 // 0x0008  Read/write   8          0x20            Timer control register
+        __O  uint32_t       INTCLR    ;                 // 0x000C  Write        - -                        Timer interrupt clear
+        __I  uint32_t       RIS       ;                 // 0x0010  Read         1          0x0             Timer raw interrupt status
+        __I  uint32_t       MIS       ;                 // 0x0014  Read         1          0x0             Timer masked interrupt status
+        __IO uint32_t       BGLOAD    ;                 // 0x0018  Read/write   32         0x00000000      Background load value for Timer
+
+} ICP_TIMER_T, *PICP_TIMER_T ;
+
+// -------- ICP_TIMER_LOAD : (LOAD Offset: 0x00) Load value for Timer -------- 
+// -------- ICP_TIMER_VALUE : (LOAD Offset: 0x04) The current value for Timer -------- 
+// -------- ICP_TIMER_CONTROL : (CONTROL Offset: 0x04) Timer control register -------- 
+#define ICP_TIMER_CONTROL_MASK                 ((unsigned int)0x0F << 0)        // Timer control mask
+    #define ICP_TIMER_CONTROL_ENABLE           ((unsigned int)0x01 << 7)        // Timer enable: 0 = disabled 1 = enabled.
+    #define ICP_TIMER_CONTROL_MODE             ((unsigned int)0x01 << 6)        // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count..
+    #define ICP_TIMER_CONTROL_IE               ((unsigned int)0x01 << 5)        // Interrupt enable.
+    #define ICP_TIMER_CONTROL_R                ((unsigned int)0x01 << 4)        // Unused, always write as 0s.
+    #define ICP_TIMER_CONTROL_PRESCALE_MASK    ((unsigned int)0x03 << 2)        // Prescale divisor
+    #define ICP_TIMER_CONTROL_PRESCALE_NONE    ((unsigned int)0x00 << 2)        // 
+    #define ICP_TIMER_CONTROL_PRESCALE_16      ((unsigned int)0x01 << 2)        // 
+    #define ICP_TIMER_CONTROL_PRESCALE_256     ((unsigned int)0x02 << 2)        // 
+#define ICP_TIMER_CONTROL_TIMER_SIZE           ((unsigned int)0x01 << 1)        // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0.
+#define ICP_TIMER_CONTROL_ONE_SHOT             ((unsigned int)0x01 << 0)        // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode
+// -------- ICP_TIMER_INTCLR : (INTCLR Offset: 0x0C) Timer interrupt clear -------- 
+// -------- ICP_TIMER_RIS : (RIS Offset: 0x10) Timer raw interrupt status -------- 
+// -------- ICP_TIMER_MIS : (MIS Offset: 0x14) Timer masked interrupt status -------- 
+#define ICP_TIMER_INT                          ((unsigned int)0x01 << 0)        // Interrupt
+// -------- ICP_TIMER_BGLOAD : (BGLOAD Offset: 0x18) Timer masked interrupt status -------- 
+
+
+// *****************************************************************************
+// INTEGRATORCP PIC
+// *****************************************************************************
+typedef struct ICP_PIC_S {
+                                                    // offset  read/write   word size  reset           Description
+        __I  uint32_t       IRQ_STATUS      ;           // 0x0000  Read         22                         IRQ gated interrupt status
+        __I  uint32_t       IRQ_RAWSTAT     ;           // 0x0004  Read         22                         IRQ raw interrupt status
+        __IO uint32_t       IRQ_ENABLESET   ;           // 0x0008  Read/write   22                         IRQ enable set
+        __O  uint32_t       IRQ_ENABLECLR   ;           // 0x000C  Write        22                         IRQ enable clear
+        __IO uint32_t       INT_SOFTSET     ;           // 0x0010  Read/write   16                         Software interrupt set
+        __O  uint32_t       INT_SOFTCLR     ;           // 0x0014  Write        16                         Software interrupt clear
+             uint32_t       RESERVED[2]     ;           // 0x0018  
+        __I  uint32_t       FIQ_STATUS      ;           // 0x0020  Read         22                         FIQ gated interrupt status
+        __I  uint32_t       FIQ_RAWSTAT     ;           // 0x0024  Read         22                         FIQ raw interrupt status
+        __IO uint32_t       FIQ_ENABLESET   ;           // 0x0028  Read/write   22                         FIQ enable set
+        __O  uint32_t       FIQ_ENABLECLR   ;           // 0x002C  Write-only   22                         FIQ enable clear
+
+} ICP_PIC_T, *PICP_PIC_T ;
+
+// -------- ICP_PIC_IRQ_STATUS : (IRQ_STATUS Offset: 0x00) IRQ gated interrupt status -------- 
+// -------- ICP_PIC_IRQ_RAWSTAT : (IRQ_RAWSTAT Offset: 0x04) IRQ raw interrupt status -------- 
+// -------- ICP_PIC_IRQ_ENABLESET : (IRQ_ENABLESET Offset: 0x08) IRQ enable set -------- 
+// -------- ICP_PIC_IRQ_ENABLECLR : (IRQ_ENABLECLR Offset: 0x0C) IRQ enable clear -------- 
+#define ICP_PIC_IRQ_MASK                       ((unsigned int)0x3FFFFF << 0)    // IRQ mask
+    #define ICP_PIC_IRQ_TIMERINT2              ((unsigned int)0x01 << 7)        // TIMERINT2 Counter-timer 2 interrupt
+    #define ICP_PIC_IRQ_TIMERINT1              ((unsigned int)0x01 << 6)        // TIMERINT1 Counter-timer 1 interrupt
+    #define ICP_PIC_IRQ_TIMERINT0              ((unsigned int)0x01 << 5)        // TIMERINT0 Counter-timer 0 interrupt
+    #define ICP_PIC_IRQ_SOFTINT                ((unsigned int)0x01 << 0)        // OFTINT Software interrupt
+// -------- ICP_PIC_INT_SOFTSET : (INT_SOFTSET Offset: 0x10) Software interrupt set -------- 
+// -------- ICP_PIC_INT_SOFTCLR : (INT_SOFTCLR Offset: 0x14) Software interrupt clear -------- 
+
+
+
+/* module definitions */
+#define BOARD_BASE_ADDRESS_TIMER_0             0x13000000 
+#define BOARD_BASE_ADDRESS_PIC                 0x14000000 
+
+extern ICP_TIMER_T*       const                board_timer_0 ;
+extern ICP_PIC_T*         const                board_pic ;
+
+
+/* Function prototypes */
+extern int              low_level_init (void) ;
+
+
+#endif /* __MODULES_H__ */

ports/arm/platforms/qemu_integratorcp/run_test.exp

@@ -0,0 +1,39 @@
+#!/usr/bin/env expect
+
+# Expect script to run an automated test within QEMU and check for successful
+# completion.
+#
+# Arguments: <path_to_qemu> <test_elf_file>
+#
+# Returns 0 on successful test run within QEMU, 1 on failure
+
+
+# Start the test
+spawn [lindex $argv 0] -M integratorcp -semihosting -nographic -kernel [lindex $argv 1]
+
+# Expect to see the test starting within 10 seconds
+set timeout 10
+
+# Wait for the test to start ("Go")
+expect {
+	"Go\r\n" {
+		puts "Test started"
+
+		# The test could take up to 3 minutes to complete once started
+		set timeout 180
+
+		# Now expect to see "Pass" or "Fail" within 3 minutes
+		expect {
+			"Pass\r\n" { puts "Test passed"; exit 0 }
+			"Fail\r\n" { puts "Test failed"; exit 1 }
+			timeout { puts "Test timed out without completing"; exit 1 }
+		}
+	}
+
+	timeout {
+		# Didn't receive "Go" within 10 seconds
+		puts "Test failed to start ('Go' not seen)"
+		exit 1
+	}
+}
+

ports/arm/platforms/qemu_integratorcp/startup.s

@@ -0,0 +1,47 @@
+.section .vectors, "x"
+
+.global __interrupt_vector_table
+.extern __irq_stack_top__
+.extern __fiq_stack_top__
+.extern __svc_stack_top__
+
+
+.equ USR_MODE,            0x10
+.equ FIQ_MODE,            0x11
+.equ IRQ_MODE,            0x12
+.equ SVC_MODE,            0x13
+.equ ABT_MODE,            0x17
+.equ UND_MODE,            0x1B
+.equ SYS_MODE,            0x1F
+
+.equ I_BIT,               0x80            /* when I bit is set, IRQ is disabled */
+.equ F_BIT,               0x40            /* when F bit is set, FIQ is disabled */
+
+
+__interrupt_vector_table:
+
+  B Reset_Handler /* Reset */
+  ldr PC,=null_handler  /* Undefined */
+  ldr PC,=null_handler  /* SWI */
+  ldr PC,=null_handler  /* Prefetch Abort */
+  ldr PC,=null_handler  /* Data Abort */
+  ldr PC,=null_handler  /* reserved */
+  ldr PC,=archIRQHandler/* IRQ */
+  ldr PC,=null_handler  /* FIQ */
+ 
+
+Reset_Handler:
+
+    MSR CPSR_c,#(IRQ_MODE | I_BIT | F_BIT)
+    LDR sp,=__irq_stack_top__ /* set the IRQ stack pointer */
+    MSR CPSR_c,#(FIQ_MODE | I_BIT | F_BIT)
+    LDR sp,=__fiq_stack_top__ /* set the FIQ stack pointer */
+    MSR CPSR_c,#(SVC_MODE | I_BIT | F_BIT)
+    LDR sp,=__svc_stack_top__ /* set the SVC stack pointer */
+
+    BL low_level_init
+    BL _mainCRTStartup
+
+
+  B .
+

ports/arm/platforms/qemu_integratorcp/system.ld

@@ -0,0 +1,89 @@
+
+ENTRY(__interrupt_vector_table)
+
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000
+    sram (rwx) : ORIGIN = 0x00020000, LENGTH = 0x00020000
+}
+
+
+EXTERN(__interrupt_vector_table);
+
+
+C_STACK_SIZE = 512;
+IRQ_STACK_SIZE = 256;
+FIQ_STACK_SIZE = 256;
+SVC_STACK_SIZE = 512;
+ABT_STACK_SIZE = 256;
+UND_STACK_SIZE = 256;
+
+SECTIONS
+{
+
+    
+    .text :
+    {
+        *(.vectors)
+        /* Startup assembly */
+        *(.startup)
+        *(.init)
+
+        /* Rest of the code (C) */
+        *(.text)
+        *(.rodata)
+        *(.rodata*)
+
+        _end_text = .;
+    } >flash
+
+    .data :
+    {
+        _start_data = .;
+        *(.data)
+        _end_data = .;
+    } >sram
+
+    .bss :
+    {
+        _start_bss = .;
+        __bss_start__ = . ;
+        *(.bss)
+    } >sram
+
+    . = ALIGN(4);
+    _end_bss = .;
+    __bss_end__ = . ;
+
+    . = ALIGN(256);
+    
+    .stack : {
+    __stack_start__ = . ;
+    . += IRQ_STACK_SIZE;
+    . = ALIGN (4);
+    __irq_stack_top__ = . ;
+    . += FIQ_STACK_SIZE;
+    . = ALIGN (4);
+    __fiq_stack_top__ = . ;
+    . += SVC_STACK_SIZE;
+    . = ALIGN (4);
+    __svc_stack_top__ = . ;
+    . += ABT_STACK_SIZE;
+    . = ALIGN (4);
+    __abt_stack_top__ = . ;
+    . += UND_STACK_SIZE;
+    . = ALIGN (4);
+    __und_stack_top__ = . ;
+    . += C_STACK_SIZE;
+    . = ALIGN (4);
+    __c_stack_top__ = . ;
+    __stack_end__ = .;
+    } >sram 
+
+}
+__end__ = .;
+_end = .;
+PROVIDE(end = .);
+
+heap_top = ORIGIN(sram) + LENGTH(sram) - 4;

ports/arm/platforms/qemu_integratorcp/uart.c

@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/** 
+ * \file
+ * Simple polled UART implementation for non-hosted compiler toolchains.
+ *
+ *
+ * This is only required for non-hosted toolchains which don't implement
+ * stdout automatically for use within QEMU.
+ */
+
+#include "atom.h"
+#include "atommutex.h"
+#include "atomport.h"
+#include "uart.h"
+
+
+/* Constants */
+
+/** UART0 registers base address */
+#define UART0_ADDR       0x16000000
+
+/** FR Register bits */
+#define UART_FR_RXFE     0x10
+#define UART_FR_TXFF     0x20
+
+/** UART register access macros */
+#define UART_DR(baseaddr) (*(unsigned int *)(baseaddr))
+#define UART_FR(baseaddr) (*(((unsigned int *)(baseaddr))+6))
+
+
+/* Local data */
+
+/*
+ * Semaphore for single-threaded access to UART device
+ */
+static ATOM_MUTEX uart_mutex;
+
+/*
+ * Initialised flag
+ */
+static int initialised = FALSE;
+
+
+/* Forward declarations */
+static int uart_init (void);
+
+
+/**
+ * \b uart_init
+ *
+ * Initialisation of UART driver. Creates a mutex that enforces
+ * single-threaded access to the UART. We poll register bits
+ * to check when space is available, which would not otherwise
+ * be thread-safe.
+ *
+ * @retval ATOM_OK Success
+ * @retval ATOM_ERROR Failed to create mutex
+ */
+static int uart_init (void)
+{
+    int status;
+
+    /* Check we are not already initialised */
+    if (initialised == FALSE)
+    {
+        /* Create a mutex for single-threaded UART access */
+        if (atomMutexCreate (&uart_mutex) != ATOM_OK)
+        {
+            /* Mutex creation failed */
+            status = ATOM_ERROR;
+        }
+        else
+        {
+            /* Success */
+            initialised = TRUE;
+            status = ATOM_OK;
+        }
+    }
+
+    /* Finished */
+    return (status);
+}
+
+
+/**
+ * \b uart_read
+ *
+ * Simple polled UART read.
+ *
+ * @param[in] ptr Pointer to receive buffer
+ * @param[in] len Max bytes to read
+ *
+ * @retval Number of bytes read
+ *
+ */
+int uart_read (char *ptr, int len)
+{
+    int todo = 0;
+
+    /* Check we are initialised */
+    if (initialised == FALSE)
+    {
+        uart_init();
+    }
+
+    /* Check parameters */
+    if ((ptr == NULL) || (len == 0))
+    {
+        return 0;
+    }
+
+    /* Block thread on private access to the UART */
+    if (atomMutexGet(&uart_mutex, 0) == ATOM_OK)
+    {
+        /* Wait for not-empty */
+        while(UART_FR(UART0_ADDR) & UART_FR_RXFE)
+            ;
+
+        /* Read first byte */
+        *ptr++ = UART_DR(UART0_ADDR);
+
+        /* Loop over remaining bytes until empty */
+        for (todo = 1; todo < len; todo++)
+        {
+            /* Quit if receive FIFO empty */
+            if(UART_FR(UART0_ADDR) & UART_FR_RXFE)
+            {
+                break;
+            }
+
+            /* Read next byte */
+            *ptr++ = UART_DR(UART0_ADDR);
+        }
+
+        /* Return mutex access */
+        atomMutexPut(&uart_mutex);
+    }
+
+    /* Return number of bytes read */
+    return todo;
+}
+
+
+/**
+ * \b uart_write
+ *
+ * Simple polled UART write.
+ *
+ * @param[in] ptr Pointer to write buffer
+ * @param[in] len Number of bytes to write
+ *
+ * @retval Number of bytes written
+ */
+int uart_write (const char *ptr, int len)
+{
+    int todo;
+
+    /* Check we are initialised */
+    if (initialised == FALSE)
+    {
+        uart_init();
+    }
+
+    /* Check parameters */
+    if ((ptr == NULL) || (len == 0))
+    {
+        return 0;
+    }
+
+    /* Block thread on private access to the UART */
+    if (atomMutexGet(&uart_mutex, 0) == ATOM_OK)
+    {
+        /* Loop through all bytes to write */
+        for (todo = 0; todo < len; todo++)
+        {
+            /* Wait for empty */
+            while(UART_FR(UART0_ADDR) & UART_FR_TXFF)
+                ;
+
+            /* Write byte to UART */
+            UART_DR(UART0_ADDR) = *ptr++;
+        }
+
+        /* Return mutex access */
+        atomMutexPut(&uart_mutex);
+    }
+
+    /* Return bytes-written count */
+    return len;
+}
+
+
+/**
+ * \b uart_write_halt
+ *
+ * Simple polled UART write for handling critical failures
+ * by printing out a message on the UART and looping forever.
+ * Can be called from interrupt (unlike the standard
+ * uart_write()) but is not thread-safe because it cannot
+ * take the thread-safety mutex, and hence is only useful for
+ * a last-resort catastrophic debug message.
+ *
+ * @param[in] ptr Pointer to write string
+ */
+void uart_write_halt (const char *ptr)
+{
+    /* Check parameters */
+    if (ptr != NULL)
+    {
+        /* Loop through all bytes until NULL terminator encountered */
+        while (*ptr != '\0')
+        {
+            /* Wait for empty */
+            while(UART_FR(UART0_ADDR) & UART_FR_TXFF)
+                ;
+
+            /* Write byte to UART */
+            UART_DR(UART0_ADDR) = *ptr++;
+        }
+    }
+
+    /* Loop forever */
+    while (1)
+        ;
+
+}

ports/arm/platforms/qemu_integratorcp/uart.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_UART_H
+#define __ATOM_UART_H
+
+/* UART driver APIs */
+extern int uart_read (char *ptr, int len);
+extern int uart_write (const char *ptr, int len);
+extern void uart_write_halt (const char *ptr);
+
+#endif /* __ATOM_UART_H */

ports/arm/syscalls.c

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/** 
+ * \file
+ * Syscalls implementation for stdio and heap management.
+ *
+ *
+ * Simple implementation of syscalls.c for ARM compiler toolchains built
+ * without newlib. Allows usage of printf() and friends as well as heap
+ * allocation.
+ *
+ * NOTE: Platform/BSP must implement uart_read() and uart_write().
+ *
+ * NOTE: Platform/BSP linker script must define "end" and "heap_top" which are
+ * the heap base and top respectively.
+ *
+ * No file table is implemented. All file read/write operations are carried
+ * out on the UART driver, regardless of file descriptor.
+ *
+ * Mostly based on code from http://balau82.wordpress.com
+ *
+ */
+
+#include <sys/stat.h>
+#include "uart.h"
+
+
+/** 
+ * Define all functions as weak so that the functions in this file will
+ * only be used if the compiler toolchain doesn't already provide them.
+ */
+extern int _close(int file) __attribute__((weak));
+extern int _fstat(int file, struct stat *st) __attribute__((weak));
+extern int _isatty(int file) __attribute__((weak));
+extern int _lseek(int file, int ptr, int dir) __attribute__((weak));
+extern int _open(const char *name, int flags, int mode) __attribute__((weak));
+extern int _read(int file, char *ptr, int len) __attribute__((weak));
+extern caddr_t _sbrk(int incr) __attribute__((weak));
+extern int _write(int file, char *ptr, int len) __attribute__((weak));
+
+
+/**
+ * \b _close
+ *
+ * Simple stub implementation with no file table. All parameters ignored.
+ *
+ */
+int _close(int file)
+{
+    return -1;
+}
+
+
+/**
+ * \b _fstat
+ *
+ * Simple stub implementation. Always return character device.
+ *
+ */
+int _fstat(int file, struct stat *st)
+{
+    /* Only UART supported, always return character-oriented device file */
+    st->st_mode = S_IFCHR;
+    return 0;
+}
+
+
+/**
+ * \b _isatty
+ *
+ * Simple stub implementation. Only UART supported so TTY always true.
+ *
+ */
+int _isatty(int file)
+{
+    return 1;
+}
+
+
+/**
+ * \b _lseek
+ *
+ * Simple stub implementation. All parameters ignored.
+ *
+ */
+int _lseek(int file, int ptr, int dir)
+{
+    return 0;
+}
+
+
+/**
+ * \b _open
+ *
+ * Simple stub implementation with no file table. All parameters ignored.
+ *
+ */
+int _open(const char *name, int flags, int mode)
+{
+    return -1;
+}
+
+
+/**
+ * \b _read
+ *
+ * Simple read file implementation. Ignores file descriptor parameter
+ * and always reads from the UART driver.
+ *
+ * @param[in] file File descriptor (parameter ignored)
+ * @param[in] ptr Pointer to receive buffer
+ * @param[in] len Max bytes to read
+ *
+ * @retval Number of bytes read
+ */
+int _read(int file, char *ptr, int len)
+{
+    /* Read from the UART driver, regardless of file descriptor */
+    return (uart_read (ptr, len));
+}
+
+
+/**
+ * \b _write
+ *
+ * Simple write file implementation. Ignores file descriptor parameter
+ * and always writes to the UART driver.
+ *
+ * @param[in] file File descriptor (parameter ignored)
+ * @param[in] ptr Pointer to write buffer
+ * @param[in] len Number of bytes to write
+ *
+ * @retval Number of bytes written
+ */
+int _write(int file, char *ptr, int len)
+{
+    /* Write to the UART driver, regardless of file descriptor */
+    return (uart_write (ptr, len));
+}
+
+
+/**
+ * \b _sbrk
+ *
+ * Simple heap implementation.
+ *
+ * The platform/BSP must define "end" and "heap_top" which are the heap
+ * base and top respectively.
+ *
+ * @param[in] incr Chunk size
+ *
+ * @retval Pointer to allocated chunk start
+ */
+caddr_t _sbrk(int incr)
+{
+ extern char end;          /* Defined by the linker */
+ extern char heap_top;     /* Defined by the linker */
+ static char *heap_end = 0;
+ char *prev_heap_end;
+
+    /* First time in, initialise heap base using definition from linker script */
+    if (heap_end == 0)
+    {
+        heap_end = &end;
+    }
+
+    /* Save the previous heap base */
+    prev_heap_end = heap_end;
+
+    /* Check we have not passed the heap top */
+    if (heap_end + incr > &heap_top)
+    {
+        /* Heap top reached, failed to allocate */
+        return (caddr_t)0;
+    }
+
+    /* New heap base */
+    heap_end += incr;
+
+    /* Return pointer to previous base (where our allocation starts) */
+    return (caddr_t)prev_heap_end;
+}
+

ports/arm/tests-main.c

@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2013, Kelvin Lawson. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+
+#include "atom.h"
+#include "atomport-private.h"
+#include "atomtests.h"
+#include "atomtimer.h"
+
+
+/* Constants */
+
+/*
+ * Idle thread stack size
+ *
+ * This needs to be large enough to handle any interrupt handlers
+ * and callbacks called by interrupt handlers (e.g. user-created
+ * timer callbacks) as well as the saving of all context when
+ * switching away from this thread.
+ */
+#define IDLE_STACK_SIZE_BYTES       512
+
+
+/*
+ * Main thread stack size
+ *
+ * Note that this is not a required OS kernel thread - you will replace
+ * this with your own application thread.
+ *
+ * In this case the Main thread is responsible for calling out to the
+ * test routines. Once a test routine has finished, the test status is
+ * printed out on the UART and the thread remains running in a loop.
+ *
+ * The Main thread stack generally needs to be larger than the idle
+ * thread stack, as not only does it need to store interrupt handler
+ * stack saves and context switch saves, but the application main thread
+ * will generally be carrying out more nested function calls and require
+ * stack for application code local variables etc.
+ *
+ * 1KB might be adequate but if using printf() then at least 2KB would be
+ * prudent otherwise the stdio functions otherwise stack overruns are
+ * likely. Nearly 2KB was seen to be used on the toolchain used for
+ * development.
+ */
+#define MAIN_STACK_SIZE_BYTES       4096
+
+
+/* Local data */
+
+/* Application threads' TCBs */
+static ATOM_TCB main_tcb;
+
+/* Main thread's stack area */
+static uint8_t main_thread_stack[MAIN_STACK_SIZE_BYTES];
+
+/* Idle thread's stack area */
+static uint8_t idle_thread_stack[IDLE_STACK_SIZE_BYTES];
+
+
+/* Forward declarations */
+static void main_thread_func (uint32_t data);
+
+
+/**
+ * \b main
+ *
+ * Program entry point.
+ *
+ * Creates an application thread and starts the OS.
+ */
+
+int main ( void )
+{
+    int8_t status;
+
+    /**
+     * Note: to protect OS structures and data during initialisation,
+     * interrupts must remain disabled until the first thread
+     * has been restored. They are reenabled at the very end of
+     * the first thread restore, at which point it is safe for a
+     * reschedule to take place.
+     */
+
+    /**
+     * Initialise the OS before creating our threads.
+     */
+    status = atomOSInit(&idle_thread_stack[0], IDLE_STACK_SIZE_BYTES, TRUE);
+    if (status == ATOM_OK)
+    {
+        /* Create an application thread */
+        status = atomThreadCreate(&main_tcb,
+                     TEST_THREAD_PRIO, main_thread_func, 0,
+                     &main_thread_stack[0],
+                     MAIN_STACK_SIZE_BYTES,
+                     TRUE);
+        if (status == ATOM_OK)
+        {
+            /**
+             * First application thread successfully created. It is
+             * now possible to start the OS. Execution will not return
+             * from atomOSStart(), which will restore the context of
+             * our application thread and start executing it.
+             *
+             * Note that interrupts are still disabled at this point.
+             * They will be enabled as we restore and execute our first
+             * thread in archFirstThreadRestore().
+             */
+            atomOSStart();
+        }
+    }
+
+    while (1)
+        ;
+
+    /* There was an error starting the OS if we reach here */
+    return (0);
+}
+
+
+/**
+ * \b main_thread_func
+ *
+ * Entry point for main application thread.
+ *
+ * This is the first thread that will be executed when the OS is started.
+ *
+ * @param[in] data Unused (optional thread entry parameter)
+ *
+ * @return None
+ */
+static void main_thread_func (uint32_t data)
+{
+    uint32_t test_status;
+
+    /* Put a message out on the UART */
+    printf ("Go\n");
+
+    /* Start test. All tests use the same start API. */
+    test_status = test_start();
+
+    /* Check main thread stack usage (if enabled) */
+#ifdef ATOM_STACK_CHECKING
+    if (test_status == 0)
+    {
+        uint32_t used_bytes, free_bytes;
+
+        /* Check idle thread stack usage */
+        if (atomThreadStackCheck (&main_tcb, &used_bytes, &free_bytes) == ATOM_OK)
+        {
+            /* Check the thread did not use up to the end of stack */
+            if (free_bytes == 0)
+            {
+                printf ("Main stack overflow\n");
+                test_status++;
+            }
+
+            /* Log the stack usage */
+#ifdef TESTS_LOG_STACK_USAGE
+            printf ("MainUse:%d\n", (int)used_bytes);
+#endif
+        }
+
+    }
+#endif
+
+    /* Log final status */
+    if (test_status == 0)
+    {
+        printf ("Pass\n");
+    }
+    else
+    {
+        printf ("Fail(%d)\n", (int)test_status);
+    }
+
+}

ports/armv7a/Makefile

@@ -0,0 +1,149 @@
+##########################################
+# Toplevel makefile for all ARM7a boards #
+##########################################
+
+# Build directory
+ifdef O
+ build_dir=$(shell readlink -f $(O))
+else
+ build_dir=$(CURDIR)/build
+endif
+
+# Source directory
+src_dir=$(CURDIR)
+
+# Configuration
+ifndef CPU
+CPU=cortex-a8
+endif
+ifndef BOARD
+BOARD=pb-a8
+endif
+CC=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+# Enable stack-checking. WARNING: the full automated test suite currently
+# requires a little over 1KB RAM with stack-checking enabled. If you are 
+# using a device with 1KB internal SRAM and no external SRAM then you
+# must disable stack-checking to run all of the automated tests.
+#STACK_CHECK=true
+
+# Location of atomthreads sources
+board_dir=$(src_dir)/$(BOARD)
+kernel_dir=$(src_dir)/../../kernel
+tests_dir=$(src_dir)/../../tests
+
+# Check if verbosity is ON for build process
+VERBOSE_DEFAULT    := 0
+CMD_PREFIX_DEFAULT := @
+ifdef VERBOSE
+	ifeq ("$(origin VERBOSE)", "command line")
+		VB := $(VERBOSE)
+	else
+		VB := $(VERBOSE_DEFAULT)
+	endif
+else
+	VB := $(VERBOSE_DEFAULT)
+endif
+ifeq ($(VB), 1)
+	V :=
+else
+	V := $(CMD_PREFIX_DEFAULT)
+endif
+
+# object files
+objs = arm_irq.o 
+objs += arm_main.o 
+objs += atomport.o
+objs += arm_entry.o
+objs += atomport-asm.o 
+
+# include board makefile for board specific objects
+-include $(board_dir)/Makefile
+
+# library object files
+objs += printk.o 
+objs += string.o 
+objs += vsprintf.o
+
+# Kernel object files
+objs += atomkernel.o 
+objs += atomsem.o 
+objs += atommutex.o 
+objs += atomtimer.o 
+objs += atomqueue.o
+
+# Collection of built objects (excluding test applications)
+build_objs = $(foreach obj,$(objs),$(build_dir)/$(obj))
+
+# Target application filenames .elf for each test object
+tobjs = $(notdir $(patsubst %.c,%.o,$(wildcard $(tests_dir)/*.c)))
+telfs = $(patsubst %.o,%.elf,$(tobjs))
+tbins = $(patsubst %.o,%.bin,$(tobjs))
+build_tobjs = $(foreach tobj,$(tobjs),$(build_dir)/$(tobj))
+build_telfs = $(foreach telf,$(telfs),$(build_dir)/$(telf))
+build_tbins = $(foreach tbin,$(tbins),$(build_dir)/$(tbin))
+
+# GCC flags
+CFLAGS= -g \
+	-Wall \
+	-Werror \
+	-mcpu=$(CPU) \
+	-nostdinc \
+	-nostdlib \
+	-nodefaultlibs \
+	-fno-builtin \
+	-I$(src_dir) \
+	-I$(board_dir) \
+	-I$(kernel_dir) \
+	-I$(tests_dir)
+
+# Enable stack-checking (disable if not required)
+ifeq ($(STACK_CHECK),true)
+CFLAGS += -DATOM_STACK_CHECKING
+endif
+
+# All
+.PHONY: all
+all: $(build_tbins) $(build_telfs) $(build_tobjs) $(build_objs) Makefile
+
+$(build_dir)/%.bin: $(build_dir)/%.elf
+	$(V)mkdir -p `dirname $@`
+	$(if $(V), @echo " (OBJCOPY)   $(subst $(build_dir)/,,$@)")
+	$(V)$(OBJCOPY) -O binary $< $@
+
+$(build_dir)/%.elf: $(build_dir)/%.o $(build_objs) $(board_dir)/linker.ld
+	$(V)mkdir -p `dirname $@`
+	$(if $(V), @echo " (ELF)       $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) $(CFLAGS) $(build_objs) $< -static-libgcc -lgcc  -Wl -T $(board_dir)/linker.ld -o $@
+
+$(build_dir)/%.o: $(src_dir)/%.S
+	$(V)mkdir -p `dirname $@`
+	$(if $(V), @echo " (AS)        $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) $(CFLAGS) -D__ASSEMBLY__ -I`dirname $<` -c $< -o $@
+
+$(build_dir)/%.o: $(src_dir)/%.c
+	$(V)mkdir -p `dirname $@`
+	$(if $(V), @echo " (CC)        $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) $(CFLAGS) $(CFLAGS) -I`dirname $<` -c $< -o $@
+
+$(build_dir)/%.o: $(kernel_dir)/%.c
+	$(V)mkdir -p `dirname $@`
+	$(if $(V), @echo " (CC)        $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) $(CFLAGS) $(CFLAGS) -I`dirname $<` -c $< -o $@
+
+$(build_dir)/%.o: $(tests_dir)/%.c
+	$(V)mkdir -p `dirname $@`
+	$(if $(V), @echo " (CC)        $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) $(CFLAGS) $(CFLAGS) -I`dirname $<` -c $< -o $@
+
+# Clean
+.PHONY: clean
+clean:
+	rm -rf doxygen-kernel
+	rm -rf doxygen-armv7a
+	rm -rf $(build_dir)
+# Docs
+.PHONY: doxygen
+doxygen:
+	doxygen $(kernel_dir)/Doxyfile
+	doxygen ./Doxyfile

ports/armv7a/README

@@ -0,0 +1,14 @@
+CROSS_COMPILE=/opt/arm-2009q3/bin/arm-none-eabi-
+export CROSS_COMPILE
+
+qemu-system-arm -M realview-pb-a8 -serial stdio -kernel build/kern2.elf
+
+Following are the steps to add new board <abc> under armv7a port:
+1. Create a directory under ports/armv7a with name <abc>
+2. Add linker.ld in ports/armv7a/<abc> (similar to the one in ports/armv7a/pb-a8)
+3. Add arm_pic.h, arm_timer.h, and arm_uart.h in ports/armv7a/<abc> (similar to the one in ports/armv7a/pb-a8)
+4. Add .c files in ports/armv7a/<abc> to implement the board specific functions expected in arm_pic.h, arm_timer.h, and arm_uart.h
+5. Add Makefile in ports/armv7a/<abc> (similar to the one in ports/armv7a/pb-a8) to build board specific objects corresponding to the .c files added in step 4.
+5. To build atomthreads for <abc> board use following command "make BOARD=<abc>" with ports/armv7a as current directory.
+
+Port contributed by Anup Patel (http://brainfault.blogspot.com).

ports/armv7a/arm_asm_macro.h

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ARM_ASM_MACRO_H__
+#define __ARM_ASM_MACRO_H__
+
+#include <arm_defines.h>
+
+#ifdef __ASSEMBLY__
+
+.macro SET_CURRENT_FLAGS flags, treg
+	mrs	\treg, cpsr
+	orr	\treg, \treg, #(\flags)
+	msr 	cpsr, \treg
+.endm
+
+.macro SET_CURRENT_MODE mode
+	cps	#(\mode)
+.endm
+
+.macro SET_CURRENT_STACK new_stack
+	ldr	sp, \new_stack
+.endm
+
+.macro START_EXCEPTION_HANDLER irqname, lroffset
+	.align 5
+\irqname:
+	sub	lr, lr, #\lroffset
+.endm
+
+/* Save User Registers */
+.macro PUSH_USER_REGS
+	str     lr, [sp, #-4]!;         /* Push the return address */
+	sub     sp, sp, #(4*15);        /* Adjust the stack pointer */
+	stmia   sp, {r0-r12};           /* Push user mode registers */
+	add     r0, sp, #(4*13);        /* Adjust the stack pointer */
+	stmia   r0, {r13-r14}^;         /* Push user mode registers */
+	mov     r0, r0;                 /* NOP for previous inst */
+	mrs     r0, spsr_all;           /* Put the SPSR on the stack */
+	str     r0, [sp, #-4]!
+.endm
+
+/* If came from priviledged mode then push banked registers */
+.macro PUSH_BANKED_REGS skip_lable
+	mov	r4, r0
+	and	r0, r0, #CPSR_MODE_MASK
+	cmp	r0, #CPSR_MODE_USER
+	beq	\skip_lable
+	add	r1, sp, #(4*14)
+	mrs	r5, cpsr
+	orr	r4, r4, #(CPSR_IRQ_DISABLED | CPSR_FIQ_DISABLED)
+	msr	cpsr, r4
+	str	sp, [r1, #0]
+	str	lr, [r1, #4]
+	msr	cpsr, r5
+	\skip_lable:
+.endm
+
+/* Call C function to handle exception */
+.macro CALL_EXCEPTION_CFUNC cfunc
+	mov	r0, sp
+	bl	\cfunc
+.endm
+
+/* If going back to priviledged mode then pull banked registers */
+.macro PULL_BANKED_REGS skip_lable
+	ldr     r0, [sp, #0]
+	mov	r4, r0
+	and	r0, r0, #CPSR_MODE_MASK
+	cmp	r0, #CPSR_MODE_USER
+	beq	\skip_lable
+	add	r1, sp, #(4*14)
+	mrs	r5, cpsr
+	orr	r4, r4, #(CPSR_IRQ_DISABLED | CPSR_FIQ_DISABLED)
+	msr	cpsr, r4
+	ldr	sp, [r1, #0]
+	ldr	lr, [r1, #4]
+	msr	cpsr, r5
+	\skip_lable:
+.endm
+
+/* Restore User Registers */
+.macro PULL_USER_REGS
+	ldr     r0, [sp], #0x0004;      /* Get SPSR from stack */
+	msr     spsr_all, r0;
+	ldmia   sp, {r0-r14}^;          /* Restore registers (user) */
+	mov     r0, r0;                 /* NOP for previous isnt */
+	add     sp, sp, #(4*15);        /* Adjust the stack pointer */
+	ldr     lr, [sp], #0x0004       /* Pull return address */
+.endm
+
+.macro END_EXCEPTION_HANDLER
+	movs	pc, lr
+.endm
+
+#endif
+
+#endif

ports/armv7a/arm_defines.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2010, Atomthreads Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARM_DEFINES_H_
+#define __ARM_DEFINES_H_
+
+#define CPSR_VALIDBITS_MASK				0xFF0FFFFF
+#define CPSR_USERBITS_MASK				0xFFFFFC00
+#define CPSR_USERBITS_SHIFT				10
+#define CPSR_PRIVBITS_MASK				0x000003FF
+#define CPSR_PRIVBITS_SHIFT				0
+#define CPSR_MODE_MASK					0x0000001f
+#define CPSR_MODE_USER					0x00000010
+#define CPSR_MODE_FIQ					0x00000011
+#define CPSR_MODE_IRQ					0x00000012
+#define CPSR_MODE_SUPERVISOR				0x00000013
+#define CPSR_MODE_MONITOR				0x00000016
+#define CPSR_MODE_ABORT					0x00000017
+#define CPSR_MODE_UNDEFINED				0x0000001b
+#define CPSR_MODE_SYSTEM				0x0000001f
+#define CPSR_THUMB_ENABLED				(1 << 5)
+#define CPSR_FIQ_DISABLED				(1 << 6)
+#define CPSR_IRQ_DISABLED				(1 << 7)
+#define CPSR_ASYNC_ABORT_DISABLED			(1 << 8)
+#define CPSR_BE_ENABLED					(1 << 9)
+#define CPSR_IT2_MASK					0x0000FC00
+#define CPSR_IT2_SHIFT					10
+#define CPSR_GE_MASK					0x000F0000
+#define CPSR_GE_SHIFT					16
+#define CPSR_JAZZLE_ENABLED				(1 << 24)
+#define CPSR_IT1_MASK					0x06000000
+#define CPSR_IT1_SHIFT					25
+#define CPSR_COND_OVERFLOW_MASK				(1 << 28)
+#define CPSR_COND_OVERFLOW_SHIFT			28
+#define CPSR_COND_CARRY_MASK				(1 << 29)
+#define CPSR_COND_CARRY_SHIFT				29
+#define CPSR_COND_ZERO_MASK				(1 << 30)
+#define CPSR_COND_ZERO_SHIFT				30
+#define CPSR_COND_NEGATIVE_MASK				(1 << 31)
+#define CPSR_COND_NEGATIVE_SHIFT			31
+
+#endif /* __ARM_DEFINES_H_ */

ports/armv7a/arm_entry.S

@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_asm_macro.h>
+
+	.section .expvect, "ax", %progbits
+	.globl _start_vect
+_start_vect:	
+	ldr	pc, __reset
+	ldr	pc, __undefined_instruction
+	ldr	pc, __software_interrupt
+	ldr	pc, __prefetch_abort
+	ldr	pc, __data_abort
+	ldr	pc, __not_used
+	ldr	pc, __irq
+	ldr	pc, __fiq
+__reset:
+	.word _reset
+__undefined_instruction:
+	.word _undefined_instruction
+__software_interrupt:
+	.word _software_interrupt
+__prefetch_abort:
+	.word _prefetch_abort
+__data_abort:
+	.word _data_abort
+__not_used:
+	.word _not_used
+__irq:
+	.word _irq
+__fiq:
+	.word _fiq
+	.global _end_vect
+_end_vect:
+
+__initial_stack_end:
+	.word _initial_stack_end
+
+	.globl _reset
+_reset:
+	/* Clear a register for temporary usage */
+	mov	r8, #0
+	/* Disable IRQ & FIQ */
+	cpsid if
+	/* Set Supervisor Mode Stack */
+	SET_CURRENT_MODE CPSR_MODE_SUPERVISOR
+	SET_CURRENT_STACK __initial_stack_end
+	/* Set Undefined Mode Stack */
+	SET_CURRENT_MODE CPSR_MODE_UNDEFINED
+	SET_CURRENT_STACK __initial_stack_end
+	/* Set Abort Mode Stack */
+	SET_CURRENT_MODE CPSR_MODE_ABORT
+	SET_CURRENT_STACK __initial_stack_end
+	/* Set IRQ Mode Stack */
+	SET_CURRENT_MODE CPSR_MODE_IRQ
+	SET_CURRENT_STACK __initial_stack_end
+	/* Set FIQ Mode Stack */
+	SET_CURRENT_MODE CPSR_MODE_FIQ
+	SET_CURRENT_STACK __initial_stack_end
+	/* Set System Mode Stack */
+	SET_CURRENT_MODE CPSR_MODE_SYSTEM
+	SET_CURRENT_STACK __initial_stack_end
+	/* Set to Supervisor Mode */
+	SET_CURRENT_MODE CPSR_MODE_SUPERVISOR
+	/* Call main function */
+	bl	main
+	/* We should never reach here */
+	b	.
+
+START_EXCEPTION_HANDLER _undefined_instruction, 4
+	PUSH_USER_REGS
+	PUSH_BANKED_REGS _undefined_instruction_bankpush_skip
+	CALL_EXCEPTION_CFUNC do_undefined_instruction
+	PULL_BANKED_REGS _undefined_instruction_bankpull_skip
+	PULL_USER_REGS
+END_EXCEPTION_HANDLER
+
+START_EXCEPTION_HANDLER _software_interrupt, 4
+	PUSH_USER_REGS
+	PUSH_BANKED_REGS _software_interrupt_bankpush_skip
+	CALL_EXCEPTION_CFUNC do_software_interrupt
+	PULL_BANKED_REGS _software_interrupt_bankpull_skip
+	PULL_USER_REGS
+END_EXCEPTION_HANDLER
+
+START_EXCEPTION_HANDLER _prefetch_abort, 4
+	PUSH_USER_REGS
+	PUSH_BANKED_REGS _prefetch_abort_bankpush_skip
+	CALL_EXCEPTION_CFUNC do_prefetch_abort
+	PULL_BANKED_REGS _prefetch_abort_bankpull_skip
+	PULL_USER_REGS
+END_EXCEPTION_HANDLER
+
+START_EXCEPTION_HANDLER _data_abort, 8
+	PUSH_USER_REGS
+	PUSH_BANKED_REGS _data_abort_bankpush_skip
+	CALL_EXCEPTION_CFUNC do_data_abort
+	PULL_BANKED_REGS _data_abort_bankpull_skip
+	PULL_USER_REGS
+END_EXCEPTION_HANDLER
+
+START_EXCEPTION_HANDLER _not_used, 4
+	PUSH_USER_REGS
+	PUSH_BANKED_REGS _not_used_bankpush_skip
+	CALL_EXCEPTION_CFUNC do_not_used
+	PULL_BANKED_REGS _not_used_bankpull_skip
+	PULL_USER_REGS
+END_EXCEPTION_HANDLER
+
+START_EXCEPTION_HANDLER _irq, 4
+	PUSH_USER_REGS
+	PUSH_BANKED_REGS _irq_bankpush_skip
+	CALL_EXCEPTION_CFUNC do_irq
+	PULL_BANKED_REGS _irq_bankpull_skip
+	PULL_USER_REGS
+END_EXCEPTION_HANDLER
+
+START_EXCEPTION_HANDLER _fiq, 4
+	PUSH_USER_REGS
+	PUSH_BANKED_REGS _fiq_bankpush_skip
+	CALL_EXCEPTION_CFUNC do_fiq
+	PULL_BANKED_REGS _fiq_bankpull_skip
+	PULL_USER_REGS
+END_EXCEPTION_HANDLER
+

ports/armv7a/arm_io.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARM_IO_H_
+#define __ARM_IO_H_
+
+#include <atomport.h>
+
+static inline uint32_t arm_readl(void * addr)
+{
+	return *((uint32_t *)addr);
+}
+
+static inline void arm_writel(uint32_t data, void * addr)
+{
+	*((uint32_t *)addr) = data;
+}
+
+#endif /* __ARM_IO_H_ */

ports/armv7a/arm_irq.c

@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atom.h>
+#include <arm_config.h>
+#include <arm_pic.h>
+#include <arm_irq.h>
+
+arm_irq_handler_t irq_hndls[NR_IRQS_PBA8];
+
+void do_undefined_instruction(pt_regs_t *regs)
+{
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}
+
+void do_software_interrupt(pt_regs_t *regs)
+{
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}
+
+void do_prefetch_abort(pt_regs_t *regs)
+{
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}
+
+void do_data_abort(pt_regs_t *regs)
+{
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}
+
+void do_not_used(pt_regs_t *regs)
+{
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}
+
+void do_irq(pt_regs_t *uregs)
+{
+	int rc = 0;
+	int irq = arm_pic_active_irq();
+
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	if (-1 < irq) {
+		if (irq_hndls[irq]) {
+			rc = irq_hndls[irq](irq, uregs);
+			if (rc) {
+				while (1);
+			}
+		}
+		rc = arm_pic_ack_irq(irq);
+		if (rc) {
+			while (1);
+		}
+	}
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}
+
+void do_fiq(pt_regs_t *uregs)
+{
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}
+
+void arm_irq_init(void)
+{
+	extern uint32_t _start_vect[];
+	uint32_t *vectors = (uint32_t *)NULL;
+	uint32_t *vectors_data = vectors + CPU_IRQ_NR;
+	int vec;
+ 
+	/*
+	 * Loop through the vectors we're taking over, and copy the
+	 * vector's insn and data word.
+	 */
+	for (vec = 0; vec < CPU_IRQ_NR; vec++) {
+		vectors[vec] = _start_vect[vec];
+		vectors_data[vec] = _start_vect[vec+CPU_IRQ_NR];
+	}
+
+	/*
+	 * Check if verctors are set properly
+	 */
+	for (vec = 0; vec < CPU_IRQ_NR; vec++) {
+		if ((vectors[vec] != _start_vect[vec]) ||
+		    (vectors_data[vec] != _start_vect[vec+CPU_IRQ_NR])) {
+			/* Hang */
+			while(1);
+		}
+	}
+
+	/*
+	 * Reset irq handlers
+	 */
+	for (vec = 0; vec < NR_IRQS_PBA8; vec++) {
+		irq_hndls[vec] = NULL;
+	}
+
+	/*
+	 * Initialize Generic Interrupt Controller
+	 */
+	vec = arm_pic_init();
+	if (vec) {
+		while(1);
+	}
+}
+
+void arm_irq_register(uint32_t irq, arm_irq_handler_t hndl)
+{
+	int rc = 0;
+	if (irq < NR_IRQS_PBA8) {
+		irq_hndls[irq] = hndl;
+		if (irq_hndls[irq]) {
+			rc = arm_pic_unmask(irq);
+			if (rc) {
+				while (1);
+			}
+		}
+	}
+}
+
+void arm_irq_enable(void)
+{
+	__asm( "cpsie if" );
+}
+
+void arm_irq_disable(void)
+{
+	__asm( "cpsid if" );
+}
+
+irq_flags_t arm_irq_save(void)
+{
+	unsigned long retval;
+
+	asm volatile (" mrs     %0, cpsr\n\t" " cpsid   i"	/* Syntax CPSID <iflags> {, #<p_mode>}
+								 * Note: This instruction is supported 
+								 * from ARM6 and above
+								 */
+		      :"=r" (retval)::"memory", "cc");
+
+	return retval;
+}
+
+void arm_irq_restore(irq_flags_t flags)
+{
+	asm volatile (" msr     cpsr_c, %0"::"r" (flags)
+		      :"memory", "cc");
+}
+

ports/armv7a/arm_irq.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARM_IRQ_H
+#define __ARM_IRQ_H
+
+#include "atomport.h"
+#include "atomport-private.h"
+#include "arm_defines.h"
+
+typedef int (*arm_irq_handler_t) (uint32_t irq_no, pt_regs_t * regs);
+
+#define CPU_IRQ_NR					8
+
+/** IRQ Numbers */
+#define ARM_RESET_IRQ					0
+#define ARM_UNDEF_INST_IRQ				1
+#define ARM_SOFT_IRQ					2
+#define ARM_PREFETCH_ABORT_IRQ				3
+#define ARM_DATA_ABORT_IRQ				4
+#define ARM_NOT_USED_IRQ				5
+#define ARM_EXTERNAL_IRQ				6
+#define ARM_EXTERNAL_FIQ				7
+
+void arm_irq_init(void);
+void arm_irq_register(uint32_t irq_no, arm_irq_handler_t hndl);
+void arm_irq_enable(void);
+void arm_irq_disable(void);
+irq_flags_t arm_irq_save(void);
+void arm_irq_restore(irq_flags_t flags);
+
+#endif /* __ARM_IRQ_H */

ports/armv7a/arm_main.c

@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "atom.h"
+#include "atomport.h"
+#include "atomtests.h"
+#include "atomtimer.h"
+#include "system.h"
+#include "arm_irq.h"
+#include "arm_timer.h"
+#include "arm_uart.h"
+
+/* Constants */
+
+/*
+ * Idle thread stack size
+ *
+ * This needs to be large enough to handle any interrupt handlers
+ * and callbacks called by interrupt handlers (e.g. user-created
+ * timer callbacks) as well as the saving of all context when
+ * switching away from this thread.
+ *
+ * In this case, the idle stack is allocated on the BSS via the
+ * idle_thread_stack[] byte array.
+ */
+#define IDLE_STACK_SIZE_BYTES       8192
+
+
+/*
+ * Main thread stack size
+ *
+ * Note that this is not a required OS kernel thread - you will replace
+ * this with your own application thread.
+ *
+ * In this case the Main thread is responsible for calling out to the
+ * test routines. Once a test routine has finished, the test status is
+ * printed out on the UART and the thread remains running in a loop
+ * flashing a LED.
+ *
+ * The Main thread stack generally needs to be larger than the idle
+ * thread stack, as not only does it need to store interrupt handler
+ * stack saves and context switch saves, but the application main thread
+ * will generally be carrying out more nested function calls and require
+ * stack for application code local variables etc.
+ *
+ * With all OS tests implemented to date on the AVR, the Main thread
+ * stack has not exceeded 198 bytes. To allow all tests to run we set
+ * a minimum main thread stack size of 204 bytes. This may increase in
+ * future as the codebase changes but for the time being is enough to
+ * cope with all of the automated tests.
+ */
+#define MAIN_STACK_SIZE_BYTES       8192
+
+
+/*
+ * Startup code stack
+ *
+ * Some stack space is required at initial startup for running the main()
+ * routine. This stack space is only temporarily required at first bootup
+ * and is no longer required as soon as the OS is started. By default
+ * GCC sets this to the top of RAM (RAMEND) and it grows down from there.
+ * Because we only need this temporarily, though, it would be wasteful to
+ * set aside a region at the top of RAM which is not used during runtime.
+ *
+ * What we do here is to reuse part of the idle thread's stack during
+ * initial startup. As soon as we enter the main() routine we move the
+ * stack pointer to half-way down the idle thread's stack. This is used
+ * temporarily while calls are made to atomOSInit(), atomThreadCreate()
+ * and atomOSStart(). Once the OS is started this stack area is no
+ * longer required, and can be used for its original purpose (for the
+ * idle thread's stack).
+ *
+ * This does mean, however, that we cannot monitor the stack usage of the
+ * idle thread. Stack usage is monitored by prefilling the stack with a
+ * known value, and we are obliterating some of that prefilled area by
+ * using it as our startup stack, so we cannot use the stack-checking API
+ * to get a true picture of idle thread stack usage. If you wish to 
+ * monitor idle thread stack usage for your applications then you are
+ * free to use a different region for the startup stack (e.g. set aside
+ * an area permanently, or place it somewhere you know you can reuse
+ * later in the application). For the time being, this method gives us a
+ * simple way of reducing the memory consumption without having to add
+ * any special AVR-specific considerations to the automated test
+ * applications.
+ *
+ * This optimisation was required to allow some of the larger automated
+ * test modules to run on devices with 1KB of RAM. You should avoid doing
+ * this if you can afford to set aside 64 bytes or so, or if you are
+ * writing your own applications in which you have further control over
+ * where data is located.
+ */
+
+
+/* Local data */
+
+/* Application threads' TCBs */
+static ATOM_TCB main_tcb;
+
+/* Main thread's stack area */
+static uint8_t main_thread_stack[MAIN_STACK_SIZE_BYTES];
+
+/* Idle thread's stack area */
+static uint8_t idle_thread_stack[IDLE_STACK_SIZE_BYTES];
+
+/* Forward declarations */
+static void main_thread_func (uint32_t data);
+
+/**
+ * \b main
+ *
+ * Program entry point.
+ *
+ * Sets up the AVR hardware resources (system tick timer interrupt) necessary
+ * for the OS to be started. Creates an application thread and starts the OS.
+ */
+
+int main ( void )
+{
+    int8_t status;
+
+    /**
+     * Note: to protect OS structures and data during initialisation,
+     * interrupts must remain disabled until the first thread
+     * has been restored. They are reenabled at the very end of
+     * the first thread restore, at which point it is safe for a
+     * reschedule to take place.
+     */
+
+    /**
+     * Initialise the OS before creating our threads.
+     *
+     * Note that we tell the OS that the idle stack is half its actual
+     * size. This prevents it prefilling the bottom half with known
+     * values for stack-checkig purposes, which we cannot allow because
+     * we are temporarily using it for our own stack. The remainder will
+     * still be available once the OS is started, this only prevents the
+     * OS from prefilling it.
+     *
+     * If you are not reusing the idle thread's stack during startup then
+     * you should pass in the correct size here.
+     */
+    status = atomOSInit(&idle_thread_stack[0],
+			IDLE_STACK_SIZE_BYTES, 0);
+    if (status == ATOM_OK)
+    {
+		arm_irq_init();
+
+		arm_timer_init(SYSTEM_TICKS_PER_SEC);
+
+		arm_uart_init();
+
+        /* Create an application thread */
+        status = atomThreadCreate(&main_tcb,
+                     TEST_THREAD_PRIO, main_thread_func, 0,
+                     &main_thread_stack[0],
+				  MAIN_STACK_SIZE_BYTES, 0);
+        if (status == ATOM_OK)
+        {
+			arm_timer_enable();
+
+            /**
+             * First application thread successfully created. It is
+             * now possible to start the OS. Execution will not return
+             * from atomOSStart(), which will restore the context of
+             * our application thread and start executing it.
+             *
+             * Note that interrupts are still disabled at this point.
+             * They will be enabled as we restore and execute our first
+             * thread in archFirstThreadRestore().
+             */
+            atomOSStart();
+        }
+    }
+
+    while (1)
+        ;
+
+    /* There was an error starting the OS if we reach here */
+    return (0);
+}
+
+
+/**
+ * \b main_thread_func
+ *
+ * Entry point for main application thread.
+ *
+ * This is the first thread that will be executed when the OS is started.
+ *
+ * @param[in] data Unused (optional thread entry parameter)
+ *
+ * @return None
+ */
+static void main_thread_func (uint32_t data)
+{
+	/* Put a message out on the UART */
+	printk("Test Started ... ");
+	if (test_start() != 0) {
+		printk("FAILED!\n");
+	} else {
+		printk("SUCCESS!\n");
+	}
+	printk("Reset your board !!!!!");
+	/* Test finished so just hang !!! */
+	while (1)
+		;
+}

ports/armv7a/atomport-asm.S

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011, Anup Patel for Atomthreads Project.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_asm_macro.h>
+
+	.section .text
+
+/**
+ * int archSetJump(pt_regs_t *regs)
+ */
+	.globl archSetJump
+archSetJump:
+	add	r0, r0, #(4 * 16)
+	str	lr, [r0]
+	sub	r0, r0, #(4 * 14)
+	stm	r0, {r1-r14}
+	mov	r0, r0 /* NOP */
+	str	r2, [r1]
+	mov	r2, #0
+	sub	r0, r0, #4
+	str	r2, [r0]
+	mrs	r2, cpsr_all
+	sub	r0, r0, #4
+	str	r2, [r0]
+	ldr	r2, [r1]
+	mov	r0, #1
+	bx	lr
+
+/**
+ * void archLongJump(pt_regs_t *regs)
+ */
+	.globl archLongJump
+archLongJump:
+	mrs	r1, cpsr_all
+	SET_CURRENT_MODE CPSR_MODE_IRQ
+	mov	sp, r0
+	SET_CURRENT_MODE CPSR_MODE_FIQ
+	mov	sp, r0
+	msr	cpsr_all, r1
+	ldr     r1, [r0], #4 /* Get CPSR from stack */
+	orr	r2, r1, #(CPSR_IRQ_DISABLED | CPSR_FIQ_DISABLED)
+	msr	cpsr_all, r2
+	msr	spsr_all, r1
+	ldm	r0, {r0-r15}^
+	mov	r0, r0 /* NOP */
+

ports/armv7a/atomport-private.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2011, Atomthreads Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOMPORT_PRIVATE_H_
+#define __ATOMPORT_PRIVATE_H_
+
+typedef unsigned int irq_flags_t;
+typedef unsigned int virtual_addr_t;
+typedef unsigned int virtual_size_t;
+typedef unsigned int physical_addr_t;
+typedef unsigned int physical_size_t;
+typedef unsigned int clock_freq_t;
+typedef unsigned long long jiffies_t;
+
+struct pt_regs {
+	uint32_t cpsr;	// Current Program Status
+	uint32_t gpr[13];	// R0 - R12
+	uint32_t sp;
+	uint32_t lr;
+	uint32_t pc;
+} __attribute ((packed)) ;
+typedef struct pt_regs pt_regs_t;
+
+/* Function prototypes */
+extern int archSetJump(pt_regs_t *regs, uint32_t *tmp);
+extern void archLongJump(pt_regs_t *regs);
+
+#endif /* __ATOMPORT_PRIVATE_H_ */

ports/armv7a/atomport-tests.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_PORT_TESTS_H
+#define __ATOM_PORT_TESTS_H
+
+/* Include Atomthreads kernel API */
+#include "atom.h"
+
+/* Prerequisite include for ATOMLOG() macro (via printf) */
+#include "printk.h"
+
+/* Logger macro for viewing test results */
+#define ATOMLOG printk
+#define _STR
+
+/* Default thread stack size (in bytes) */
+#define TEST_THREAD_STACK_SIZE      8192
+
+/* Uncomment to enable logging of stack usage to UART */
+/* #define TESTS_LOG_STACK_USAGE */
+
+#endif /* __ATOM_PORT_TESTS_H */
+

ports/armv7a/atomport.c

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2011, Anup Patel for Atomthreads Project.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "atom.h"
+#include "atomport.h"
+#include "atomport-private.h"
+#include "string.h"
+#include "arm_defines.h"
+
+/**
+ * This function initialises each thread's stack during creation, before the
+ * thread is first run. New threads are scheduled in using the same
+ * context-switch function used for threads which were previously scheduled
+ * out, therefore this function should set up a stack context which looks
+ * much like a thread which has been scheduled out and had its context saved.
+ * We fill part of the stack with those registers which are involved in the
+ * context switch, including appropriate stack or register contents to cause
+ * the thread to branch to its entry point function when it is scheduled in.
+ *
+ * Interrupts should also be enabled whenever a thread is restored, hence
+ * ports may wish to explicitly include the interrupt-enable register here
+ * which will be restored when the thread is scheduled in. Other methods
+ * can be used to enable interrupts, however, without explicitly storing
+ * it in the thread's context.
+ */
+void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top,
+                            void (*entry_point)(UINT32),
+                            UINT32 entry_param)
+{
+	int i;
+	pt_regs_t *regs = (pt_regs_t *)((uint32_t)stack_top - sizeof(pt_regs_t));
+
+	tcb_ptr->sp_save_ptr = stack_top;
+	regs->cpsr = CPSR_COND_ZERO_MASK |
+		    CPSR_ASYNC_ABORT_DISABLED | CPSR_MODE_SUPERVISOR;
+	regs->gpr[0] = entry_param;
+	for (i = 1; i < 13; i++) {
+		regs->gpr[i] = 0x0;
+	}
+	regs->sp = (uint32_t)stack_top - sizeof(pt_regs_t) - 1024;
+	regs->lr = (uint32_t)entry_point;
+	regs->pc = (uint32_t)entry_point;
+}
+
+
+/**
+ * archFirstThreadRestore(ATOM_TCB *new_tcb)
+ *
+ * This function is responsible for restoring and starting the first
+ * thread the OS runs. It expects to find the thread context exactly
+ * as it would be if a context save had previously taken place on it.
+ * The only real difference between this and the archContextSwitch()
+ * routine is that there is no previous thread for which context must
+ * be saved.
+ *
+ * The final action this function must do is to restore interrupts.
+ */
+void archFirstThreadRestore(ATOM_TCB *new_tcb)
+{
+	pt_regs_t *regs = (pt_regs_t *)((uint32_t)new_tcb->sp_save_ptr 
+							- sizeof(pt_regs_t));
+	archLongJump(regs);
+}
+
+/**
+ * Function that performs the contextSwitch. Whether its a voluntary release
+ * of CPU by thread or a pre-emption, under both conditions this function is
+ * called. The signature is as follows:
+ *
+ * archContextSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb)
+ */
+void archContextSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb)
+{
+	uint32_t tmp = 0x0, lr = 0x0;
+	pt_regs_t *old_regs = (pt_regs_t *)((uint32_t)old_tcb->sp_save_ptr
+							- sizeof(pt_regs_t));
+	pt_regs_t *new_regs = (pt_regs_t *)((uint32_t)new_tcb->sp_save_ptr
+							- sizeof(pt_regs_t));
+	asm volatile (" mov %0, lr\n\t" :"=r"(lr):);
+	if (archSetJump(old_regs, &tmp)) {
+		old_regs->lr = lr;
+		archLongJump(new_regs);
+	}
+}
+

ports/armv7a/atomport.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2011, Anup Patel for Atomthreads Project.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_PORT_H
+#define __ATOM_PORT_H
+
+
+/* Required number of system ticks per second (normally 100 for 10ms tick) */
+#define SYSTEM_TICKS_PER_SEC            1000
+
+/**
+ * Definition of NULL. stddef.h not available on this platform.
+ */
+#define NULL ((void *)(0))
+
+/* Size of each stack entry / stack alignment size (32 bits on ARMv7A) */
+#define STACK_ALIGN_SIZE                sizeof(uint32_t)
+
+/**
+ * Architecture-specific types.
+ * Provide stdint.h style types.
+ */
+#define uint8_t   unsigned char
+#define uint16_t  unsigned short
+#define uint32_t  unsigned int
+#define uint64_t  unsigned long long
+#define int8_t    signed char
+#define int16_t   signed short
+#define int32_t   signed int
+#define int64_t   long long
+#define size_t    unsigned long
+#define POINTER   void *
+#define UINT32    uint32_t
+
+/**
+ * Critical region protection: this should disable interrupts
+ * to protect OS data structures during modification. It must
+ * allow nested calls, which means that interrupts should only
+ * be re-enabled when the outer CRITICAL_END() is reached.
+ */
+#include "arm_irq.h"
+#include "atomport-private.h"
+#define CRITICAL_STORE		irq_flags_t status_flags
+#define CRITICAL_START()	status_flags = arm_irq_save();
+#define CRITICAL_END()		arm_irq_restore(status_flags);
+
+/* Uncomment to enable stack-checking */
+/* #define ATOM_STACK_CHECKING */
+
+
+#endif /* __ATOM_PORT_H */

ports/armv7a/pb-a8/Makefile

@@ -0,0 +1,9 @@
+##########################
+# Board specific objects #
+##########################
+
+# board object files
+objs += pb-a8/arm_pic.o 
+objs += pb-a8/arm_timer.o 
+objs += pb-a8/arm_uart.o 
+

ports/armv7a/pb-a8/arm_config.h

@@ -0,0 +1,147 @@
+/**
+ * Copyright (c) 2011 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arm_config.h
+ * @version 1.0
+ * @author Anup Patel (anup@brainfault.org)
+ * @brief ARM Platform Configuration Header
+ */
+#ifndef _ARM_CONFIG_H__
+#define _ARM_CONFIG_H__
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PBA8_UART0_BASE		0x10009000	/* UART 0 */
+#define REALVIEW_PBA8_UART1_BASE		0x1000A000	/* UART 1 */
+#define REALVIEW_PBA8_UART2_BASE		0x1000B000	/* UART 2 */
+#define REALVIEW_PBA8_UART3_BASE		0x1000C000	/* UART 3 */
+#define REALVIEW_PBA8_SSP_BASE			0x1000D000	/* Synchronous Serial Port */
+#define REALVIEW_PBA8_WATCHDOG0_BASE		0x1000F000	/* Watchdog 0 */
+#define REALVIEW_PBA8_WATCHDOG_BASE		0x10010000	/* watchdog interface */
+#define REALVIEW_PBA8_TIMER0_1_BASE		0x10011000	/* Timer 0 and 1 */
+#define REALVIEW_PBA8_TIMER2_3_BASE		0x10012000	/* Timer 2 and 3 */
+#define REALVIEW_PBA8_GPIO0_BASE		0x10013000	/* GPIO port 0 */
+#define REALVIEW_PBA8_RTC_BASE			0x10017000	/* Real Time Clock */
+#define REALVIEW_PBA8_TIMER4_5_BASE		0x10018000	/* Timer 4/5 */
+#define REALVIEW_PBA8_TIMER6_7_BASE		0x10019000	/* Timer 6/7 */
+#define REALVIEW_PBA8_SCTL_BASE			0x1001A000	/* System Controller */
+#define REALVIEW_PBA8_CLCD_BASE			0x10020000	/* CLCD */
+#define REALVIEW_PBA8_ONB_SRAM_BASE		0x10060000	/* On-board SRAM */
+#define REALVIEW_PBA8_DMC_BASE			0x100E0000	/* DMC configuration */
+#define REALVIEW_PBA8_SMC_BASE			0x100E1000	/* SMC configuration */
+#define REALVIEW_PBA8_CAN_BASE			0x100E2000	/* CAN bus */
+#define REALVIEW_PBA8_GIC_CPU_BASE		0x1E000000	/* Generic interrupt controller CPU interface */
+#define REALVIEW_PBA8_FLASH0_BASE		0x40000000
+#define REALVIEW_PBA8_FLASH0_SIZE		SZ_64M
+#define REALVIEW_PBA8_FLASH1_BASE		0x44000000
+#define REALVIEW_PBA8_FLASH1_SIZE		SZ_64M
+#define REALVIEW_PBA8_ETH_BASE			0x4E000000	/* Ethernet */
+#define REALVIEW_PBA8_USB_BASE			0x4F000000	/* USB */
+#define REALVIEW_PBA8_GIC_DIST_BASE		0x1E001000	/* Generic interrupt controller distributor */
+#define REALVIEW_PBA8_LT_BASE			0xC0000000	/* Logic Tile expansion */
+#define REALVIEW_PBA8_SDRAM6_BASE		0x70000000	/* SDRAM bank 6 256MB */
+#define REALVIEW_PBA8_SDRAM7_BASE		0x80000000	/* SDRAM bank 7 256MB */
+
+#define REALVIEW_PBA8_SYS_PLD_CTRL1		0x74
+
+/*
+ * PBA8 PCI regions
+ */
+#define REALVIEW_PBA8_PCI_BASE			0x90040000	/* PCI-X Unit base */
+#define REALVIEW_PBA8_PCI_IO_BASE		0x90050000	/* IO Region on AHB */
+#define REALVIEW_PBA8_PCI_MEM_BASE		0xA0000000	/* MEM Region on AHB */
+
+#define REALVIEW_PBA8_PCI_BASE_SIZE		0x10000	/* 16 Kb */
+#define REALVIEW_PBA8_PCI_IO_SIZE		0x1000	/* 4 Kb */
+#define REALVIEW_PBA8_PCI_MEM_SIZE		0x20000000	/* 512 MB */
+
+/*
+ * Irqs
+ */
+#define IRQ_PBA8_GIC_START			32
+
+/* L220
+#define IRQ_PBA8_L220_EVENT	(IRQ_PBA8_GIC_START + 29)
+#define IRQ_PBA8_L220_SLAVE	(IRQ_PBA8_GIC_START + 30)
+#define IRQ_PBA8_L220_DECODE	(IRQ_PBA8_GIC_START + 31)
+*/
+
+/*
+ * PB-A8 on-board gic irq sources
+ */
+#define IRQ_PBA8_WATCHDOG	(IRQ_PBA8_GIC_START + 0)	/* Watchdog timer */
+#define IRQ_PBA8_SOFT		(IRQ_PBA8_GIC_START + 1)	/* Software interrupt */
+#define IRQ_PBA8_COMMRx		(IRQ_PBA8_GIC_START + 2)	/* Debug Comm Rx interrupt */
+#define IRQ_PBA8_COMMTx		(IRQ_PBA8_GIC_START + 3)	/* Debug Comm Tx interrupt */
+#define IRQ_PBA8_TIMER0_1	(IRQ_PBA8_GIC_START + 4)	/* Timer 0/1 (default timer) */
+#define IRQ_PBA8_TIMER2_3	(IRQ_PBA8_GIC_START + 5)	/* Timer 2/3 */
+#define IRQ_PBA8_GPIO0		(IRQ_PBA8_GIC_START + 6)	/* GPIO 0 */
+#define IRQ_PBA8_GPIO1		(IRQ_PBA8_GIC_START + 7)	/* GPIO 1 */
+#define IRQ_PBA8_GPIO2		(IRQ_PBA8_GIC_START + 8)	/* GPIO 2 */
+								/* 9 reserved */
+#define IRQ_PBA8_RTC		(IRQ_PBA8_GIC_START + 10)	/* Real Time Clock */
+#define IRQ_PBA8_SSP		(IRQ_PBA8_GIC_START + 11)	/* Synchronous Serial Port */
+#define IRQ_PBA8_UART0		(IRQ_PBA8_GIC_START + 12)	/* UART 0 on development chip */
+#define IRQ_PBA8_UART1		(IRQ_PBA8_GIC_START + 13)	/* UART 1 on development chip */
+#define IRQ_PBA8_UART2		(IRQ_PBA8_GIC_START + 14)	/* UART 2 on development chip */
+#define IRQ_PBA8_UART3		(IRQ_PBA8_GIC_START + 15)	/* UART 3 on development chip */
+#define IRQ_PBA8_SCI		(IRQ_PBA8_GIC_START + 16)	/* Smart Card Interface */
+#define IRQ_PBA8_MMCI0A		(IRQ_PBA8_GIC_START + 17)	/* Multimedia Card 0A */
+#define IRQ_PBA8_MMCI0B		(IRQ_PBA8_GIC_START + 18)	/* Multimedia Card 0B */
+#define IRQ_PBA8_AACI		(IRQ_PBA8_GIC_START + 19)	/* Audio Codec */
+#define IRQ_PBA8_KMI0		(IRQ_PBA8_GIC_START + 20)	/* Keyboard/Mouse port 0 */
+#define IRQ_PBA8_KMI1		(IRQ_PBA8_GIC_START + 21)	/* Keyboard/Mouse port 1 */
+#define IRQ_PBA8_CHARLCD	(IRQ_PBA8_GIC_START + 22)	/* Character LCD */
+#define IRQ_PBA8_CLCD		(IRQ_PBA8_GIC_START + 23)	/* CLCD controller */
+#define IRQ_PBA8_DMAC		(IRQ_PBA8_GIC_START + 24)	/* DMA controller */
+#define IRQ_PBA8_PWRFAIL	(IRQ_PBA8_GIC_START + 25)	/* Power failure */
+#define IRQ_PBA8_PISMO		(IRQ_PBA8_GIC_START + 26)	/* PISMO interface */
+#define IRQ_PBA8_DoC		(IRQ_PBA8_GIC_START + 27)	/* Disk on Chip memory controller */
+#define IRQ_PBA8_ETH		(IRQ_PBA8_GIC_START + 28)	/* Ethernet controller */
+#define IRQ_PBA8_USB		(IRQ_PBA8_GIC_START + 29)	/* USB controller */
+#define IRQ_PBA8_TSPEN		(IRQ_PBA8_GIC_START + 30)	/* Touchscreen pen */
+#define IRQ_PBA8_TSKPAD		(IRQ_PBA8_GIC_START + 31)	/* Touchscreen keypad */
+
+/* ... */
+#define IRQ_PBA8_PCI0		(IRQ_PBA8_GIC_START + 50)
+#define IRQ_PBA8_PCI1		(IRQ_PBA8_GIC_START + 51)
+#define IRQ_PBA8_PCI2		(IRQ_PBA8_GIC_START + 52)
+#define IRQ_PBA8_PCI3		(IRQ_PBA8_GIC_START + 53)
+
+#define IRQ_PBA8_SMC		-1
+#define IRQ_PBA8_SCTL		-1
+
+#define NR_GIC_PBA8		1
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PBA8
+ */
+#define NR_IRQS_PBA8		(IRQ_PBA8_GIC_START + 64)
+
+#if !defined(ARM_GIC_NR_IRQS) || (ARM_GIC_NR_IRQS < NR_IRQS_PBA8)
+#undef ARM_GIC_NR_IRQS
+#define ARM_GIC_NR_IRQS			NR_IRQS_PBA8
+#endif
+
+#if !defined(ARM_GIC_MAX_NR) || (REALVIEW_GIC_MAX_NR < NR_GIC_PBA8)
+#undef ARM_GIC_MAX_NR
+#define ARM_GIC_MAX_NR		NR_GIC_PBA8
+#endif
+
+#endif

ports/armv7a/pb-a8/arm_pic.c

@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_config.h>
+#include <arm_io.h>
+#include <arm_pic.h>
+
+#define max(a,b)	((a) < (b) ? (b) : (a))
+
+struct gic_chip_data {
+	uint32_t irq_offset;
+	virtual_addr_t dist_base;
+	virtual_addr_t cpu_base;
+};
+
+static struct gic_chip_data gic_data[ARM_GIC_MAX_NR];
+
+static inline void arm_gic_write(uint32_t val, virtual_addr_t addr)
+{
+	arm_writel(val, (void *)(addr));
+}
+
+static inline uint32_t arm_gic_read(virtual_addr_t addr)
+{
+	return arm_readl((void *)(addr));
+}
+
+int arm_gic_active_irq(uint32_t gic_nr)
+{
+	int ret = -1;
+
+	if (ARM_GIC_MAX_NR <= gic_nr) {
+		return -1;
+	}
+
+	ret = arm_gic_read(gic_data[gic_nr].cpu_base +
+				GIC_CPU_INTACK) & 0x3FF;
+	ret += gic_data[gic_nr].irq_offset;
+
+	return ret;
+}
+
+int arm_gic_ack_irq(uint32_t gic_nr, uint32_t irq)
+{
+	uint32_t mask = 1 << (irq % 32);
+	uint32_t gic_irq;
+
+	if (ARM_GIC_MAX_NR <= gic_nr) {
+		return -1;
+	}
+
+	if (irq < gic_data[gic_nr].irq_offset) {
+		return -1;
+	}
+
+	gic_irq = irq - gic_data[gic_nr].irq_offset;
+
+	arm_gic_write(mask, gic_data[gic_nr].dist_base + 
+				GIC_DIST_ENABLE_CLEAR + (gic_irq / 32) * 4);
+	arm_gic_write(gic_irq, gic_data[gic_nr].cpu_base + GIC_CPU_EOI);
+	arm_gic_write(mask, gic_data[gic_nr].dist_base + 
+				GIC_DIST_ENABLE_SET + (gic_irq / 32) * 4);
+
+	return 0;
+}
+
+int arm_gic_mask(uint32_t gic_nr, uint32_t irq)
+{
+	uint32_t mask = 1 << (irq % 32);
+	uint32_t gic_irq;
+
+	if (ARM_GIC_MAX_NR <= gic_nr) {
+		return -1;
+	}
+
+	if (irq < gic_data[gic_nr].irq_offset) {
+		return -1;
+	}
+
+	gic_irq = irq - gic_data[gic_nr].irq_offset;
+
+	arm_gic_write(mask, gic_data[gic_nr].dist_base +
+			   GIC_DIST_ENABLE_CLEAR + (gic_irq / 32) * 4);
+
+	return 0;
+}
+
+int arm_gic_unmask(uint32_t gic_nr, uint32_t irq)
+{
+	uint32_t mask = 1 << (irq % 32);
+	uint32_t gic_irq;
+
+	if (ARM_GIC_MAX_NR <= gic_nr) {
+		return -1;
+	}
+
+	if (irq < gic_data[gic_nr].irq_offset) {
+		return -1;
+	}
+
+	gic_irq = irq - gic_data[gic_nr].irq_offset;
+
+	arm_gic_write(mask, gic_data[gic_nr].dist_base +
+			   GIC_DIST_ENABLE_SET + (gic_irq / 32) * 4);
+
+	return 0;
+}
+
+int arm_gic_dist_init(uint32_t gic_nr, virtual_addr_t base, uint32_t irq_start)
+{
+	unsigned int max_irq, i;
+	uint32_t cpumask = 1 << 0;	/*smp_processor_id(); */
+
+	if (ARM_GIC_MAX_NR <= gic_nr) {
+		return -1;
+	}
+
+	cpumask |= cpumask << 8;
+	cpumask |= cpumask << 16;
+
+	gic_data[gic_nr].dist_base = base;
+	gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
+
+	arm_gic_write(0, base + GIC_DIST_CTRL);
+
+	/*
+	 * Find out how many interrupts are supported.
+	 */
+	max_irq = arm_gic_read(base + GIC_DIST_CTR) & 0x1f;
+	max_irq = (max_irq + 1) * 32;
+
+	/*
+	 * The GIC only supports up to 1020 interrupt sources.
+	 * Limit this to either the architected maximum, or the
+	 * platform maximum.
+	 */
+	if (max_irq > max(1020, ARM_GIC_NR_IRQS))
+		max_irq = max(1020, ARM_GIC_NR_IRQS);
+
+	/*
+	 * Set all global interrupts to be level triggered, active low.
+	 */
+	for (i = 32; i < max_irq; i += 16)
+		arm_gic_write(0, base + GIC_DIST_CONFIG + i * 4 / 16);
+
+	/*
+	 * Set all global interrupts to this CPU only.
+	 */
+	for (i = 32; i < max_irq; i += 4)
+		arm_gic_write(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+
+	/*
+	 * Set priority on all interrupts.
+	 */
+	for (i = 0; i < max_irq; i += 4)
+		arm_gic_write(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
+
+	/*
+	 * Disable all interrupts.
+	 */
+	for (i = 0; i < max_irq; i += 32)
+		arm_gic_write(0xffffffff,
+				   base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+
+	arm_gic_write(1, base + GIC_DIST_CTRL);
+
+	return 0;
+}
+
+int arm_gic_cpu_init(uint32_t gic_nr, virtual_addr_t base)
+{
+	if (ARM_GIC_MAX_NR <= gic_nr) {
+		return -1;
+	}
+
+	gic_data[gic_nr].cpu_base = base;
+
+	arm_gic_write(0xf0, base + GIC_CPU_PRIMASK);
+	arm_gic_write(1, base + GIC_CPU_CTRL);
+
+	return 0;
+}
+
+int arm_pic_active_irq(void)
+{
+	return arm_gic_active_irq(0);
+}
+
+int arm_pic_ack_irq(uint32_t irq)
+{
+	return arm_gic_ack_irq(0, irq);
+}
+
+int arm_pic_mask(uint32_t irq)
+{
+	return arm_gic_mask(0, irq);
+}
+
+int arm_pic_unmask(uint32_t irq)
+{
+	return arm_gic_unmask(0, irq);
+}
+
+int arm_pic_init(void)
+{
+	int rc = 0;
+
+	rc = arm_gic_dist_init(0, REALVIEW_PBA8_GIC_DIST_BASE, 
+							IRQ_PBA8_GIC_START);
+	if (rc) {
+		return rc;
+	}
+	rc = arm_gic_cpu_init(0, REALVIEW_PBA8_GIC_CPU_BASE);
+	if (rc) {
+		while(1);
+	}
+
+	return rc;
+}
+
+

ports/armv7a/pb-a8/arm_pic.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ARM_GIC_H__
+#define _ARM_GIC_H__
+
+#include <atomport.h>
+#include <arm_plat.h>
+
+#define GIC_CPU_CTRL			0x00
+#define GIC_CPU_PRIMASK			0x04
+#define GIC_CPU_BINPOINT		0x08
+#define GIC_CPU_INTACK			0x0c
+#define GIC_CPU_EOI			0x10
+#define GIC_CPU_RUNNINGPRI		0x14
+#define GIC_CPU_HIGHPRI			0x18
+
+#define GIC_DIST_CTRL			0x000
+#define GIC_DIST_CTR			0x004
+#define GIC_DIST_ENABLE_SET		0x100
+#define GIC_DIST_ENABLE_CLEAR		0x180
+#define GIC_DIST_PENDING_SET		0x200
+#define GIC_DIST_PENDING_CLEAR		0x280
+#define GIC_DIST_ACTIVE_BIT		0x300
+#define GIC_DIST_PRI			0x400
+#define GIC_DIST_TARGET			0x800
+#define GIC_DIST_CONFIG			0xc00
+#define GIC_DIST_SOFTINT		0xf00
+
+int arm_pic_active_irq(void);
+int arm_pic_ack_irq(uint32_t irq);
+int arm_pic_mask(uint32_t irq);
+int arm_pic_unmask(uint32_t irq);
+int arm_pic_init(void);
+
+#endif

ports/armv7a/pb-a8/arm_plat.h

@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ARM_PLAT_H__
+#define _ARM_PLAT_H__
+
+/*
+ * Memory definitions
+ */
+#define REALVIEW_BOOT_ROM_LO          0x30000000	/* DoC Base (64Mb)... */
+#define REALVIEW_BOOT_ROM_HI          0x30000000
+#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI	/*  Normal position */
+#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
+
+#define REALVIEW_SSRAM_BASE	/* REALVIEW_SSMC_BASE ? */
+#define REALVIEW_SSRAM_SIZE           SZ_2M
+
+/* 
+ *  SDRAM
+ */
+#define REALVIEW_SDRAM_BASE           0x00000000
+
+/* 
+ *  Logic expansion modules
+ * 
+ */
+
+/* ------------------------------------------------------------------------
+ *  RealView Registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define REALVIEW_SYS_ID_OFFSET               0x00
+#define REALVIEW_SYS_SW_OFFSET               0x04
+#define REALVIEW_SYS_LED_OFFSET              0x08
+#define REALVIEW_SYS_OSC0_OFFSET             0x0C
+
+#define REALVIEW_SYS_OSC1_OFFSET             0x10
+#define REALVIEW_SYS_OSC2_OFFSET             0x14
+#define REALVIEW_SYS_OSC3_OFFSET             0x18
+#define REALVIEW_SYS_OSC4_OFFSET             0x1C	/* OSC1 for RealView/AB */
+
+#define REALVIEW_SYS_LOCK_OFFSET             0x20
+#define REALVIEW_SYS_100HZ_OFFSET            0x24
+#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
+#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
+#define REALVIEW_SYS_FLAGS_OFFSET            0x30
+#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
+#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
+#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
+#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
+#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
+#define REALVIEW_SYS_PCICTL_OFFSET           0x44
+#define REALVIEW_SYS_MCI_OFFSET              0x48
+#define REALVIEW_SYS_FLASH_OFFSET            0x4C
+#define REALVIEW_SYS_CLCD_OFFSET             0x50
+#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
+#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
+#define REALVIEW_SYS_24MHz_OFFSET            0x5C
+#define REALVIEW_SYS_MISC_OFFSET             0x60
+#define REALVIEW_SYS_IOSEL_OFFSET            0x70
+#define REALVIEW_SYS_PROCID_OFFSET           0x84
+#define REALVIEW_SYS_TEST_OSC0_OFFSET        0xC0
+#define REALVIEW_SYS_TEST_OSC1_OFFSET        0xC4
+#define REALVIEW_SYS_TEST_OSC2_OFFSET        0xC8
+#define REALVIEW_SYS_TEST_OSC3_OFFSET        0xCC
+#define REALVIEW_SYS_TEST_OSC4_OFFSET        0xD0
+
+#define REALVIEW_SYS_BASE                    0x10000000
+#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
+#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
+#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
+#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
+#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
+
+#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
+#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
+#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
+#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
+#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
+#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
+#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
+#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
+#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
+#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
+#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
+#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
+#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
+#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
+#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
+#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
+#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
+#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
+#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
+#define REALVIEW_SYS_PROCID                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
+#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
+#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
+#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
+#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
+#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
+
+/* 
+ * Values for REALVIEW_SYS_RESET_CTRL
+ */
+#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR    0x01
+#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT   0x02
+#define REALVIEW_SYS_CTRL_RESET_DLLRESET     0x03
+#define REALVIEW_SYS_CTRL_RESET_PLLRESET     0x04
+#define REALVIEW_SYS_CTRL_RESET_POR          0x05
+#define REALVIEW_SYS_CTRL_RESET_DoC          0x06
+
+#define REALVIEW_SYS_CTRL_LED         (1 << 0)
+
+/* ------------------------------------------------------------------------
+ *  RealView control registers
+ * ------------------------------------------------------------------------
+ */
+
+/* 
+ * REALVIEW_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+
+/*
+ * REALVIEW_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
+#define REALVIEW_SYS_LOCKVAL_MASK	0xFFFF	/* write 0xA05F to enable write access */
+
+/*
+ * REALVIEW_SYS_FLASH
+ */
+#define REALVIEW_FLASHPROG_FLVPPEN	(1 << 0)	/* Enable writing to flash */
+
+/*
+ * REALVIEW_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts 
+ */
+#define REALVIEW_INTREG_WPROT        0x00	/* MMC protection status (no interrupt generated) */
+#define REALVIEW_INTREG_RI0          0x01	/* Ring indicator UART0 is asserted,              */
+#define REALVIEW_INTREG_CARDIN       0x08	/* MMCI card in detect                            */
+						/* write 1 to acknowledge and clear               */
+#define REALVIEW_INTREG_RI1          0x02	/* Ring indicator UART1 is asserted,              */
+#define REALVIEW_INTREG_CARDINSERT   0x03	/* Signal insertion of MMC card                   */
+
+/*
+ * RealView common peripheral addresses
+ */
+#define REALVIEW_SCTL_BASE            0x10001000	/* System controller */
+#define REALVIEW_I2C_BASE             0x10002000	/* I2C control */
+#define REALVIEW_AACI_BASE            0x10004000	/* Audio */
+#define REALVIEW_MMCI0_BASE           0x10005000	/* MMC interface */
+#define REALVIEW_KMI0_BASE            0x10006000	/* KMI interface */
+#define REALVIEW_KMI1_BASE            0x10007000	/* KMI 2nd interface */
+#define REALVIEW_CHAR_LCD_BASE        0x10008000	/* Character LCD */
+#define REALVIEW_SCI_BASE             0x1000E000	/* Smart card controller */
+#define REALVIEW_GPIO1_BASE           0x10014000	/* GPIO port 1 */
+#define REALVIEW_GPIO2_BASE           0x10015000	/* GPIO port 2 */
+#define REALVIEW_DMC_BASE             0x10018000	/* DMC configuration */
+#define REALVIEW_DMAC_BASE            0x10030000	/* DMA controller */
+
+/* PCI space */
+#define REALVIEW_PCI_BASE             0x41000000	/* PCI Interface */
+#define REALVIEW_PCI_CFG_BASE	      0x42000000
+#define REALVIEW_PCI_MEM_BASE0        0x44000000
+#define REALVIEW_PCI_MEM_BASE1        0x50000000
+#define REALVIEW_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define REALVIEW_PCI_BASE_SIZE	       0x01000000
+#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
+#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000	/* 32Mb */
+#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000	/* 256Mb */
+#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000	/* 256Mb */
+
+#define REALVIEW_SDRAM67_BASE         0x70000000	/* SDRAM banks 6 and 7 */
+#define REALVIEW_LT_BASE              0x80000000	/* Logic Tile expansion */
+
+/*
+ * CompactFlash
+ */
+#define REALVIEW_CF_BASE		0x18000000	/* CompactFlash */
+#define REALVIEW_CF_MEM_BASE		0x18003000	/* SMC for CompactFlash */
+
+/*
+ * Disk on Chip
+ */
+#define REALVIEW_DOC_BASE             0x2C000000
+#define REALVIEW_DOC_SIZE             (16 << 20)
+#define REALVIEW_DOC_PAGE_SIZE        512
+#define REALVIEW_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
+
+#define ERASE_UNIT_PAGES    32
+#define START_PAGE          0x80
+
+/* 
+ *  LED settings, bits [7:0]
+ */
+#define REALVIEW_SYS_LED0             (1 << 0)
+#define REALVIEW_SYS_LED1             (1 << 1)
+#define REALVIEW_SYS_LED2             (1 << 2)
+#define REALVIEW_SYS_LED3             (1 << 3)
+#define REALVIEW_SYS_LED4             (1 << 4)
+#define REALVIEW_SYS_LED5             (1 << 5)
+#define REALVIEW_SYS_LED6             (1 << 6)
+#define REALVIEW_SYS_LED7             (1 << 7)
+
+#define ALL_LEDS                  0xFF
+
+#define LED_BANK                  REALVIEW_SYS_LED
+
+/* 
+ * Control registers
+ */
+#define REALVIEW_IDFIELD_OFFSET	0x0	/* RealView build information */
+#define REALVIEW_FLASHPROG_OFFSET	0x4	/* Flash devices */
+#define REALVIEW_INTREG_OFFSET		0x8	/* Interrupt control */
+#define REALVIEW_DECODE_OFFSET		0xC	/* Fitted logic modules */
+
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      REALVIEW_BOOT_ROM_HI
+
+/*
+ * System controller bit assignment
+ */
+#define REALVIEW_REFCLK	0
+#define REALVIEW_TIMCLK	1
+
+#define REALVIEW_TIMER1_EnSel	15
+#define REALVIEW_TIMER2_EnSel	17
+#define REALVIEW_TIMER3_EnSel	19
+#define REALVIEW_TIMER4_EnSel	21
+
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  1
+
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+
+#define REALVIEW_CSR_BASE             0x10000000
+#define REALVIEW_CSR_SIZE             0x10000000
+
+#endif

ports/armv7a/pb-a8/arm_timer.c

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atom.h>
+#include <atomport.h>
+#include <arm_io.h>
+#include <arm_irq.h>
+#include <arm_config.h>
+#include <arm_plat.h>
+#include <arm_timer.h>
+
+unsigned long long jiffies;
+
+void arm_timer_enable(void)
+{
+	uint32_t ctrl;
+
+	ctrl = arm_readl((void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
+	ctrl |= TIMER_CTRL_ENABLE;
+	arm_writel(ctrl, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
+}
+
+void arm_timer_disable(void)
+{
+	uint32_t ctrl;
+
+	ctrl = arm_readl((void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
+	ctrl &= ~TIMER_CTRL_ENABLE;
+	arm_writel(ctrl, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
+}
+
+void arm_timer_clearirq(void)
+{
+	arm_writel(1, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_INTCLR));
+}
+
+int arm_timer_irqhndl(uint32_t irq_no, pt_regs_t * regs)
+{
+	/* Call the OS system tick handler */
+	atomTimerTick();
+
+	arm_timer_clearirq();
+
+	return 0;
+}
+
+int arm_timer_init(uint32_t ticks_per_sec)
+{
+	uint32_t val;
+
+	/* 
+	 * set clock frequency: 
+	 *      REALVIEW_TIMCLK is 1MHz
+	 */
+	val = arm_readl((void *)REALVIEW_SCTL_BASE) | (REALVIEW_TIMCLK << 0x1);
+	arm_writel(val, (void *)REALVIEW_SCTL_BASE);
+
+	/* Register interrupt handler */
+	arm_irq_register(IRQ_PBA8_TIMER0_1, &arm_timer_irqhndl);
+
+	val = arm_readl((void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
+	val &= ~TIMER_CTRL_ENABLE;
+	val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
+	arm_writel(val, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
+	arm_writel((1000000 / ticks_per_sec), 
+		   (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_LOAD));
+	arm_writel((1000000 / ticks_per_sec), 
+		   (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_VALUE));
+
+	return 0;
+}

ports/armv7a/pb-a8/arm_timer.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ARM_TIMER_H
+#define __ARM_TIMER_H
+
+#include <atomport.h>
+
+#define TIMER_LOAD		0x00
+#define TIMER_VALUE		0x04
+#define TIMER_CTRL		0x08
+#define TIMER_CTRL_ONESHOT	(1 << 0)
+#define TIMER_CTRL_32BIT	(1 << 1)
+#define TIMER_CTRL_DIV1		(0 << 2)
+#define TIMER_CTRL_DIV16	(1 << 2)
+#define TIMER_CTRL_DIV256	(2 << 2)
+#define TIMER_CTRL_IE		(1 << 5)	/* Interrupt Enable (versatile only) */
+#define TIMER_CTRL_PERIODIC	(1 << 6)
+#define TIMER_CTRL_ENABLE	(1 << 7)
+
+#define TIMER_INTCLR		0x0c
+#define TIMER_RIS		0x10
+#define TIMER_MIS		0x14
+#define TIMER_BGLOAD		0x18
+
+void arm_timer_enable(void);
+void arm_timer_disable(void);
+void arm_timer_clearirq(void);
+int arm_timer_init(uint32_t ticks_per_sec);
+
+#endif /* __ARM_TIMER_H */

ports/armv7a/pb-a8/arm_uart.c

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_io.h>
+#include <arm_uart.h>
+
+void arm_uart_putc(uint8_t ch)
+{
+	unsigned int base = 0x10009000;
+	if(ch=='\n') {
+		/* Wait until there is space in the FIFO */
+		while (arm_readl((void*)(base + UART_PL01x_FR)) & UART_PL01x_FR_TXFF);
+
+		/* Send the character */
+		arm_writel('\r', (void*)(base + UART_PL01x_DR));
+	}
+
+	/* Wait until there is space in the FIFO */
+	while (arm_readl((void*)(base + UART_PL01x_FR)) & UART_PL01x_FR_TXFF);
+
+	/* Send the character */
+	arm_writel(ch, (void*)(base + UART_PL01x_DR));
+}
+
+uint8_t arm_uart_getc(void)
+{
+	unsigned int base = 0x10009000;
+	uint8_t data;
+
+	/* Wait until there is data in the FIFO */
+	while (arm_readl((void*)(base + UART_PL01x_FR)) & UART_PL01x_FR_RXFE);
+
+	data = arm_readl((void*)(base + UART_PL01x_DR));
+
+	/* Check for an error flag */
+	if (data & 0xFFFFFF00) {
+		/* Clear the error */
+		arm_writel(0xFFFFFFFF, (void*)(base + UART_PL01x_ECR));
+		return -1;
+	}
+
+	return data;
+}
+
+void arm_uart_init(void)
+{
+	unsigned int base = 0x10009000;
+	unsigned int baudrate = 115200;
+	unsigned int input_clock = 24000000;
+	unsigned int divider;
+	unsigned int temp;
+	unsigned int remainder;
+	unsigned int fraction;
+
+	/* First, disable everything */
+	arm_writel(0x0, (void*)(base + UART_PL011_CR));
+
+	/*
+	 * Set baud rate
+	 *
+	 * IBRD = UART_CLK / (16 * BAUD_RATE)
+	 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) 
+	 * 	  / (16 * BAUD_RATE))
+	 */
+	temp = 16 * baudrate;
+	divider = input_clock / temp;
+	remainder = input_clock % temp;
+	temp = (8 * remainder) / baudrate;
+	fraction = (temp >> 1) + (temp & 1);
+
+	arm_writel(divider, (void*)(base + UART_PL011_IBRD));
+	arm_writel(fraction, (void*)(base + UART_PL011_FBRD));
+
+	/* Set the UART to be 8 bits, 1 stop bit, 
+	 * no parity, fifo enabled 
+	 */
+	arm_writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN),
+		(void*)(base + UART_PL011_LCRH));
+
+	/* Finally, enable the UART */
+	arm_writel((UART_PL011_CR_UARTEN | 
+			UART_PL011_CR_TXE | 
+			UART_PL011_CR_RXE),
+		(void*)(base + UART_PL011_CR));
+}
+

ports/armv7a/pb-a8/arm_uart.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARM_UART_H_
+#define __ARM_UART_H_
+
+#include <atomport.h>
+
+/*
+ * ARM PrimeCell UART's (PL010 & PL011)
+ * ------------------------------------
+ *
+ *  Definitions common to both PL010 & PL011
+ *
+ */
+#define UART_PL01x_DR                   0x00	 /*  Data read or written from the interface. */
+#define UART_PL01x_RSR                  0x04	 /*  Receive status register (Read). */
+#define UART_PL01x_ECR                  0x04	 /*  Error clear register (Write). */
+#define UART_PL01x_FR                   0x18	 /*  Flag register (Read only). */
+
+#define UART_PL01x_RSR_OE               0x08
+#define UART_PL01x_RSR_BE               0x04
+#define UART_PL01x_RSR_PE               0x02
+#define UART_PL01x_RSR_FE               0x01
+
+#define UART_PL01x_FR_TXFE              0x80
+#define UART_PL01x_FR_RXFF              0x40
+#define UART_PL01x_FR_TXFF              0x20
+#define UART_PL01x_FR_RXFE              0x10
+#define UART_PL01x_FR_BUSY              0x08
+#define UART_PL01x_FR_TMSK              (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
+
+/*
+ *  PL011 definitions
+ *
+ */
+#define UART_PL011_IBRD                 0x24
+#define UART_PL011_FBRD                 0x28
+#define UART_PL011_LCRH                 0x2C
+#define UART_PL011_CR                   0x30
+#define UART_PL011_IMSC                 0x38
+#define UART_PL011_PERIPH_ID0           0xFE0
+
+#define UART_PL011_LCRH_SPS             (1 << 7)
+#define UART_PL011_LCRH_WLEN_8          (3 << 5)
+#define UART_PL011_LCRH_WLEN_7          (2 << 5)
+#define UART_PL011_LCRH_WLEN_6          (1 << 5)
+#define UART_PL011_LCRH_WLEN_5          (0 << 5)
+#define UART_PL011_LCRH_FEN             (1 << 4)
+#define UART_PL011_LCRH_STP2            (1 << 3)
+#define UART_PL011_LCRH_EPS             (1 << 2)
+#define UART_PL011_LCRH_PEN             (1 << 1)
+#define UART_PL011_LCRH_BRK             (1 << 0)
+
+#define UART_PL011_CR_CTSEN             (1 << 15)
+#define UART_PL011_CR_RTSEN             (1 << 14)
+#define UART_PL011_CR_OUT2              (1 << 13)
+#define UART_PL011_CR_OUT1              (1 << 12)
+#define UART_PL011_CR_RTS               (1 << 11)
+#define UART_PL011_CR_DTR               (1 << 10)
+#define UART_PL011_CR_RXE               (1 << 9)
+#define UART_PL011_CR_TXE               (1 << 8)
+#define UART_PL011_CR_LPE               (1 << 7)
+#define UART_PL011_CR_IIRLP             (1 << 2)
+#define UART_PL011_CR_SIREN             (1 << 1)
+#define UART_PL011_CR_UARTEN            (1 << 0)
+
+#define UART_PL011_IMSC_OEIM            (1 << 10)
+#define UART_PL011_IMSC_BEIM            (1 << 9)
+#define UART_PL011_IMSC_PEIM            (1 << 8)
+#define UART_PL011_IMSC_FEIM            (1 << 7)
+#define UART_PL011_IMSC_RTIM            (1 << 6)
+#define UART_PL011_IMSC_TXIM            (1 << 5)
+#define UART_PL011_IMSC_RXIM            (1 << 4)
+#define UART_PL011_IMSC_DSRMIM          (1 << 3)
+#define UART_PL011_IMSC_DCDMIM          (1 << 2)
+#define UART_PL011_IMSC_CTSMIM          (1 << 1)
+#define UART_PL011_IMSC_RIMIM           (1 << 0)
+
+uint8_t arm_uart_getc(void);
+void arm_uart_putc(uint8_t ch);
+void arm_uart_init(void);
+
+#endif /* __ARM_UART_H_ */

ports/armv7a/pb-a8/linker.ld

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2011, Anup Patel. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH("arm")
+ENTRY(_start_vect)
+
+SECTIONS 
+{
+	. = 0x100000;
+
+	.text :
+ 	{
+		*(.expvect)
+		*(.text)
+		. = ALIGN(4);
+		_etext = .;
+	}
+
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+		_edata = .;
+	}
+
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+		_ebss = .;
+	}
+
+	.rodata :
+	{
+		*(.rodata .rodata.*)
+		. = ALIGN(4);
+		_erodata = .;
+	}
+
+ 	.initial_stack :
+        {
+                PROVIDE(_initial_stack_start = .);
+                . = . + 4096;
+                . = ALIGN(4);
+                PROVIDE(_initial_stack_end = .);
+        }
+}

ports/armv7a/printk.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) Himanshu Chauhan 2009-11.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its contributors 
+ *        may be used to endorse or promote products derived from this software
+ *        without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdarg.h>
+#include "system.h"
+#include "atomport.h"
+#include "printk.h"
+#include "arm_uart.h"
+
+static int8_t buf[2048];
+
+/* Uses the above routine to output a string... */
+void puts(const uint8_t *text)
+{
+	int32_t i;
+
+	for (i = 0; i < strlen((const int8_t *)text); i++) {
+		arm_uart_putc(text[i]);
+	}
+}
+
+void printk(const char *format, ...)
+{
+    va_list args;
+    int i;
+
+    va_start(args, format);
+    i = vsprintf(buf, (const int8_t *)format, args);
+    va_end(args);
+
+    puts((const uint8_t *)buf);
+}
+

ports/armv7a/printk.h

@@ -0,0 +1,42 @@
+/*
+ * This file is part of Freax kernel.
+ *
+ * Copyright (c) Himanshu Chauhan 2009-10.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its contributors 
+ *        may be used to endorse or promote products derived from this software
+ *        without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRINTK_H
+#define _PRINTK_H
+
+#include "atomport.h"
+
+extern void putch (uint8_t ch);
+extern void puts (const uint8_t *text);
+extern void printk (const char*format, ...);
+
+#endif

ports/armv7a/stdarg.h

@@ -0,0 +1,28 @@
+#ifndef _STDARG_H
+#define _STDARG_H
+
+typedef char *va_list;
+
+/* Amount of space required in an argument list for an arg of type TYPE.
+   TYPE may alternatively be an expression whose type is used.  */
+
+#define __va_rounded_size(TYPE)  \
+  (((sizeof (TYPE) + sizeof (int) - 1) / sizeof (int)) * sizeof (int))
+
+#ifndef __sparc__
+#define va_start(AP, LASTARG) 						\
+ (AP = ((char *) &(LASTARG) + __va_rounded_size (LASTARG)))
+#else
+#define va_start(AP, LASTARG) 						\
+ (__builtin_saveregs (),						\
+  AP = ((char *) &(LASTARG) + __va_rounded_size (LASTARG)))
+#endif
+
+void va_end (va_list);		/* Defined in gnulib */
+#define va_end(AP)
+
+#define va_arg(AP, TYPE)						\
+ (AP += __va_rounded_size (TYPE),					\
+  *((TYPE *) (AP - __va_rounded_size (TYPE))))
+
+#endif /* _STDARG_H */

ports/armv7a/string.c

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Himanshu Chauhan 2009-11.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its contributors 
+ *        may be used to endorse or promote products derived from this software
+ *        without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atomport.h>
+#include <system.h>
+
+void *memcpy(void *dest, const void *src, size_t count)
+{
+    const int8_t *sp = (const int8_t *)src;
+    int8_t *dp = (int8_t *)dest;
+    for(; count != 0; count--) *dp++ = *sp++;
+    return dest;
+}
+
+void *memset(void *dest, int8_t val, size_t count)
+{
+    int8_t *temp = (int8_t *)dest;
+    for( ; count != 0; count--) *temp++ = val;
+    return dest;
+}
+
+uint16_t *memsetw(uint16_t *dest, uint16_t val, size_t count)
+{
+    uint16_t *temp = (uint16_t *)dest;
+    for( ; count != 0; count--) *temp++ = val;
+    return dest;
+}
+
+size_t strlen(const int8_t *str)
+{
+    size_t retval;
+    for(retval = 0; *str != '\0'; str++) retval++;
+    return retval;
+}

ports/armv7a/string.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) Himanshu Chauhan 2009-11.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its contributors 
+ *        may be used to endorse or promote products derived from this software
+ *        without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __STRING_H
+#define __STRING_H
+
+#include <atomport.h>
+
+void *memcpy(void *dest, const void *src, size_t count);
+void *memset(void *dest, int8_t val, size_t count);
+uint16_t *memsetw(uint16_t *dest, uint16_t val, size_t count);
+size_t strlen(const int8_t *str);
+
+#endif /* __STRING_H */
+

ports/armv7a/system.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Himanshu Chauhan 2009-11.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its contributors 
+ *        may be used to endorse or promote products derived from this software
+ *        without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYSTEM_H
+#define _SYSTEM_H
+
+#include <atomport.h>
+#include <stdarg.h>
+
+extern const uint8_t *kernel_name;
+extern const uint8_t *kernel_version;
+extern const uint8_t *kernel_bdate;
+extern const uint8_t *kernel_btime;
+
+extern void *memcpy (void *dest, const void *src, size_t count);
+extern void *memset (void *dest, int8_t val, size_t count);
+extern uint16_t *memsetw (uint16_t *dest, uint16_t val, size_t count);
+extern size_t strlen (const int8_t *str);
+extern int vsprintf (int8_t *buf, const int8_t *fmt, va_list args);
+extern void init_console (void);
+extern int32_t arch_init (void);
+extern uint8_t ioreadb (void *addr);
+extern void iowriteb (void *addr, uint8_t data);
+
+#endif /* _SYSTEM_H */

ports/armv7a/vsprintf.c

@@ -0,0 +1,244 @@
+/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
+/*
+ * Wirzenius wrote this portably, Torvalds fucked it up :-)
+ * and Himanshu Fucked it up further :))
+ */
+
+#include <stdarg.h>
+#include "system.h"
+#include "atomport.h"
+
+/* we use this so that we can do without the ctype library */
+#define is_digit(c)	((c) >= '0' && (c) <= '9')
+
+static int skip_atoi(const int8_t **s)
+{
+	int i=0;
+
+	while (is_digit(**s))
+		i = i*10 + *((*s)++) - '0';
+	return i;
+}
+
+#define ZEROPAD	1		/* pad with zero */
+#define SIGN	2		/* unsigned/signed long */
+#define PLUS	4		/* show plus */
+#define SPACE	8		/* space if plus */
+#define LEFT	16		/* left justified */
+#define SPECIAL	32		/* 0x */
+#define SMALL	64		/* use 'abcdef' instead of 'ABCDEF' */
+
+/*#define do_div(n,base) ({			\
+int __res; \
+__asm__("divl %4":"=a" (n),"=d" (__res):"0" (n),"1" (0),"r" (base)); \
+__res; })*/
+
+static uint32_t do_div (int32_t *n, int32_t base)
+{
+	uint32_t remainder = *n % base;
+	*n /= base;
+	return remainder;
+}
+
+static int8_t * number(int8_t * str, int num, int32_t base, 
+		     int32_t size, int32_t precision, int32_t type)
+{
+	int8_t c,sign,tmp[36];
+	const int8_t *digits=(const int8_t *)"0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+	int32_t i;
+
+	if (type & SMALL) digits = (const int8_t *)"0123456789abcdefghijklmnopqrstuvwxyz";
+	if (type & LEFT) type &= ~ZEROPAD;
+	if (base < 2 || base > 36)
+		return 0;
+	c = (type & ZEROPAD) ? '0' : ' ' ;
+	if (type & SIGN && num < 0) {
+		sign = '-';
+		num = -num;
+	} else
+		sign = (type & PLUS) ? '+' : ((type & SPACE) ? ' ' : 0);
+	if (sign) size--;
+
+	if (type & SPECIAL) {
+	    if (base == 16) {
+		size -= 2;
+	    } else if (base == 8) {
+		size--;
+	    }
+	}
+
+	i = 0;
+	if (num == 0)
+		tmp[i++] = '0';
+	else while (num != 0)
+		tmp[i++] = digits[do_div(&num,base)];
+	if (i > precision) precision = i;
+	size -= precision;
+	if (!(type & (ZEROPAD + LEFT)))
+		while(size-- > 0)
+			*str++ = ' ';
+	if (sign)
+		*str++ = sign;
+	if (type & SPECIAL) {
+	    if (base == 8) {
+		*str++ = '0';
+	    } else if (base == 16) {
+		*str++ = '0';
+		*str++ = digits[33];
+	    }
+	}
+
+	if (!(type & LEFT))
+		while(size-- > 0)
+			*str++ = c;
+	while(i < precision--)
+		*str++ = '0';
+	while(i-- > 0)
+		*str++ = tmp[i];
+	while(size-- > 0)
+		*str++ = ' ';
+	return str;
+}
+
+int32_t vsprintf (int8_t *buf, const int8_t *fmt, va_list args)
+{
+	int32_t len;
+	int32_t i;
+	int8_t * str;
+	int8_t *s;
+	int32_t *ip;
+
+	int32_t flags;		/* flags to number() */
+
+	int32_t field_width;	/* width of output field */
+	int32_t precision;		/* min. # of digits for integers; max
+				   number of chars for from string */
+	int32_t qualifier;		/* 'h', 'l', or 'L' for integer fields */
+
+	for (str=buf ; *fmt ; ++fmt) {
+		if (*fmt != '%') {
+			*str++ = *fmt;
+			continue;
+		}
+			
+		/* process flags */
+		flags = 0;
+		repeat:
+			++fmt;		/* this also skips first '%' */
+			switch (*fmt) {
+				case '-': flags |= LEFT; goto repeat;
+				case '+': flags |= PLUS; goto repeat;
+				case ' ': flags |= SPACE; goto repeat;
+				case '#': flags |= SPECIAL; goto repeat;
+				case '0': flags |= ZEROPAD; goto repeat;
+				}
+		
+		/* get field width */
+		field_width = -1;
+		if (is_digit(*fmt))
+			field_width = skip_atoi(&fmt);
+		else if (*fmt == '*') {
+			/* it's the next argument */
+			field_width = va_arg(args, int);
+			if (field_width < 0) {
+				field_width = -field_width;
+				flags |= LEFT;
+			}
+		}
+
+		/* get the precision */
+		precision = -1;
+		if (*fmt == '.') {
+			++fmt;	
+			if (is_digit(*fmt))
+				precision = skip_atoi(&fmt);
+			else if (*fmt == '*') {
+				/* it's the next argument */
+				precision = va_arg(args, int);
+			}
+			if (precision < 0)
+				precision = 0;
+		}
+
+		/* get the conversion qualifier */
+		qualifier = -1;
+		if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') {
+			qualifier = *fmt;
+			++fmt;
+		}
+
+		switch (*fmt) {
+		case 'c':
+			if (!(flags & LEFT))
+				while (--field_width > 0)
+					*str++ = ' ';
+			*str++ = (unsigned char) va_arg(args, int);
+			while (--field_width > 0)
+				*str++ = ' ';
+			break;
+
+		case 's':
+			s = va_arg(args, int8_t *);
+			len = strlen(s);
+			if (precision < 0)
+				precision = len;
+			else if (len > precision)
+				len = precision;
+
+			if (!(flags & LEFT))
+				while (len < field_width--)
+					*str++ = ' ';
+			for (i = 0; i < len; ++i)
+				*str++ = *s++;
+			while (len < field_width--)
+				*str++ = ' ';
+			break;
+
+		case 'o':
+			str = number(str, va_arg(args, unsigned long), 8,
+				field_width, precision, flags);
+			break;
+
+		case 'p':
+			if (field_width == -1) {
+				field_width = 8;
+				flags |= ZEROPAD;
+			}
+			str = number(str,
+				(unsigned long) va_arg(args, void *), 16,
+				field_width, precision, flags);
+			break;
+
+		case 'x':
+			flags |= SMALL;
+		case 'X':
+			str = number(str, va_arg(args, unsigned long), 16,
+				field_width, precision, flags);
+			break;
+
+		case 'd':
+		case 'i':
+			flags |= SIGN;
+		case 'u':
+			str = number(str, va_arg(args, unsigned long), 10,
+				field_width, precision, flags);
+			break;
+
+		case 'n':
+			ip = va_arg(args, int32_t *);
+			*ip = (str - buf);
+			break;
+
+		default:
+			if (*fmt != '%')
+				*str++ = '%';
+			if (*fmt)
+				*str++ = *fmt;
+			else
+				--fmt;
+			break;
+		}
+	}
+	*str = '\0';
+	return str-buf;
+}

ports/avr/Makefile

@@ -15,6 +15,7 @@ CC=/usr/bin/avr-gcc
 OBJCOPY=/usr/bin/avr-objcopy
 SIZE=/usr/bin/avr-size
 UISP=/usr/bin/uisp
+SIMAVR=/tmp/run_avr
 
 # Modify this to the device name of the UART used for UISP
 UISP_DEV=/dev/ttyUSB0
@@ -28,6 +29,9 @@ PART=atmega16
 # must disable stack-checking to run all of the automated tests.
 #STACK_CHECK=true
 
+# Test programs: Log stack usage to UART (if STACK_CHECK is enabled)
+#TESTS_LOG_STACK=true
+
 # Directory for built objects
 BUILD_DIR=build
 
@@ -57,10 +61,13 @@ vpath %.hex ./$(BUILD_DIR)
 # GCC flags
 CFLAGS=-g -mmcu=$(PART) -Wall -Werror
 
-# Enable stack-checking (disable if not required)
+# Enable stack-checking options (disable if not required)
 ifeq ($(STACK_CHECK),true)
 CFLAGS += -DATOM_STACK_CHECKING
 endif
+ifeq ($(TESTS_LOG_STACK),true)
+CFLAGS += -DTESTS_LOG_STACK_USAGE
+endif
 
 
 #################
@@ -112,9 +119,17 @@ clean:
 
 # Send to STK500
 program : $(BUILD_DIR)/$(app).hex
-	$(SIZE) -C $(BUILD_DIR)/$(app).elf
+	$(SIZE) -C --mcu=$(PART) $(BUILD_DIR)/$(app).elf
 	$(UISP) -dprog=stk500 -dserial=$(UISP_DEV) -dpart=$(PART) --erase --upload --verify if=$(BUILD_DIR)/$(app).hex
 
+# Generate Doxygen documentation
 doxygen:
 	doxygen $(KERNEL_DIR)/Doxyfile
 	doxygen ./Doxyfile
+
+# Run tests within simavr simulator
+phony_sim_elfs = $(addsuffix .sim, $(TEST_ELFS))
+simtests: $(phony_sim_elfs)
+.PHONY: simtests $(phony_sim_elfs)
+$(phony_sim_elfs):
+	./run_test.exp $(SIMAVR) $(PART) $(BUILD_DIR)/$(basename $@)

ports/avr/README

@@ -1,7 +1,7 @@
 ---------------------------------------------------------------------------
 
 Library:      Atomthreads
-Author:       Kelvin Lawson <kelvinl@users.sf.net>
+Author:       Kelvin Lawson <info@atomthreads.com>
 Website:      http://atomthreads.com
 License:      BSD Revised
 
@@ -27,7 +27,7 @@ architecture-specific details such as appropriate types for 8-bit, 16-bit
 etc variables, the port's system tick frequency, and macros for performing
 interrupt lockouts / critical sections:
 
- * atomuser.h: Port-specific header required by the kernel for each port
+ * atomport.h: Port-specific header required by the kernel for each port
 
 A couple of additional source files are also included here:
 
@@ -37,7 +37,9 @@ A couple of additional source files are also included here:
 Atomthreads includes a suite of automated tests which prove the key OS
 functionality, and can be used with any architecture ports. This port
 provides an easy mechanism for building, downloading and running the test
-suite to prove the OS on your target.
+suite to prove the OS on your target. You may also use the simavr
+simulator to run the entire test suite and prove the OS without real
+hardware.
 
 The port was carried out and tested on both an ATmega16 and ATmega32
 running within an STK500 board, utilising the gcc-avr tools. It is possible
@@ -66,9 +68,10 @@ can easily replace UISP by your own favourite programmer if required.
 BUILDING THE SOURCE
 
 A Makefile is provided for building the kernel, port and automated tests.
-The full build is carried out using simply:
+The full build is carried out using the following (replacing PART by the
+ATmega device you are using):
 
- * make
+ * make PART=atmega128
 
 All objects are built into the 'build' folder under ports/avr. The build
 process builds separate target applications for each automated test, and
@@ -96,11 +99,12 @@ PROGRAMMING TO THE TARGET DEVICE
 Application HEX files which are built into the build folder can be
 downloaded to the target using:
 
- * make program app=<appname>
+ * make PART=<cpu> program app=<appname>
 
-For example to download the 'sem1.hex' test application to the target use:
+For example to download the 'sem1.hex' test application to an ATmega128
+target use:
 
- * make program app=sem1
+ * make PART=atmega128 program app=sem1
 
 This uses UISP which will write the application into flash and reset the
 CPU to start running the program automatically.
@@ -143,11 +147,11 @@ The full set of tests can be found in the top-level 'tests' folder. Each of
 these tests is built as an independent application in the 'build' folder.
 Run them individually using:
 
- * make program app=testname
+ * make PART=<cpu> program app=<testname>
 
-For example to run the 'kern1.c' test use:
+For example to run the 'kern1.c' test on an ATmega128 device use:
 
- * make program app=kern1
+ * make PART=atmega128 program app=kern1
 
 Before running the program and data size for the application is printed
 out on the terminal. You can use this to verify that your platform has
@@ -188,6 +192,35 @@ the OS, creates a main thread, and calls out to the test modules. It also
 initialises the UART driver and redirects stdout via the UART.
 
 
+---------------------------------------------------------------------------
+
+RUNNING TESTS WITHIN THE SIMAVR SIMULATOR
+
+It is also possible to run the full automated test suite in a simulator
+without programming the test applications into real hardware. This is very
+useful for quick verification of the entire test suite after making any
+software changes, and is much faster than download each test application to
+a real target.
+
+A single command runs every single test application, and checks the
+(simulated) UART output to verify that each test case passes.
+
+This requires two applications on your development PC: expect and the
+simavr simulator. You can edit the SIMAVR variable in the Makefile to point
+it at the simavr install location on your PC and then run:
+
+ * make PART=atmega128 simtests
+
+This will run every single test application within the simulator and quit
+immediately if any one test fails. You should pick an ATmega device that is
+supported by the simavr simulator: atmega128 is a good choice.
+
+The ability to run these automated tests in one command (and without real
+hardware) allows you to easily include the OS test suite in your nightly
+build or continous integration system and quickly find out if any of your
+local changes have caused any of the operating system tests to fail.
+
+
 ---------------------------------------------------------------------------
 
 WRITING APPLICATIONS
@@ -204,7 +237,10 @@ a call to your own application startup code.
 PORTING TO OTHER HARDWARE PLATFORMS
 
 If you are using a CPU other than the ATmega16, change the PART definition
-in the Makefile to your own CPU.
+in the Makefile to your own CPU, or specify the PART on the make command
+line using:
+
+ * make PART=atmega128
 
 On CPUs with multiple UARTs, the port uses UART0 to output debug 
 information. If you wish to use an alternative UART you may change the

ports/avr/atomport-asm.s

@@ -148,7 +148,7 @@ archContextSwitch:
     mov r28,r24         /* Move old_tcb_ptr param into the Y-regs so we */
     mov r29,r25         /* can access the TCB via a pointer. */
 
-    st  Y,r16           /* Store SPH/SPL to old_tcb_ptr->tcb_save_ptr which */
+    st  Y,r16           /* Store SPH/SPL to old_tcb_ptr->sp_save_ptr which */
     std Y+1,r17         /* is conveniently the first member of the TCB. */
 
 

ports/avr/atomport.h

@@ -37,10 +37,14 @@
 /* Portable uint8_t and friends available from stdint.h on this platform */
 #include <stdint.h>
 
+/* Definition of NULL is available from stddef.h on this platform */
+#include <stddef.h>
 
 /* Required number of system ticks per second (normally 100 for 10ms tick) */
 #define SYSTEM_TICKS_PER_SEC            100
 
+/* Size of each stack entry / stack alignment size (8 bits on AVR) */
+#define STACK_ALIGN_SIZE                sizeof(uint8_t)
 
 /**
  * Architecture-specific types.
@@ -50,7 +54,12 @@
 #define POINTER void *
 
 
-/* Critical region protection */
+/**
+ * Critical region protection: this should disable interrupts
+ * to protect OS data structures during modification. It must
+ * allow nested calls, which means that interrupts should only
+ * be re-enabled when the outer CRITICAL_END() is reached.
+ */
 #define CRITICAL_STORE      uint8_t sreg
 #define CRITICAL_START()    sreg = SREG; cli();
 #define CRITICAL_END()      SREG = sreg

ports/avr/run_test.exp

@@ -0,0 +1,39 @@
+#!/usr/bin/env expect
+
+# Expect script to run an automated test within the AVR simulator (simavr) and
+# check for successful completion.
+#
+# Arguments: <path_to_simavr> <cpu_part> <test_elf_file>
+#
+# Returns 0 on successful test run within AVR simulator, 1 on failure
+
+
+# Start the test
+spawn [lindex $argv 0] -m [lindex $argv 1] [lindex $argv 2]
+
+# Expect to see the test starting within 10 seconds
+set timeout 10
+
+# Wait for the test to start ("Go..")
+expect {
+	"Go.." {
+		puts "Test started"
+
+		# The test could take up to 3 minutes to complete once started
+		set timeout 180
+
+		# Now expect to see "Pass.." or "Fail" within 3 minutes
+		expect {
+			"Pass.." { puts "Test passed"; exit 0 }
+			"Fail" { puts "Test failed"; exit 1 }
+			timeout { puts "Test timed out without completing"; exit 1 }
+		}
+	}
+
+	timeout {
+		# Didn't receive "Go.." within 10 seconds
+		puts "Test failed to start ('Go' not seen)"
+		exit 1
+	}
+}
+

ports/avr/tests-main.c

@@ -71,7 +71,7 @@
  * stack for application code local variables etc.
  *
  * With all OS tests implemented to date on the AVR, the Main thread
- * stack has not exceeded 198 bytes. To allow all tests to run we set
+ * stack has not exceeded 201 bytes. To allow all tests to run we set
  * a minimum main thread stack size of 204 bytes. This may increase in
  * future as the codebase changes but for the time being is enough to
  * cope with all of the automated tests.
@@ -167,17 +167,15 @@ int main ( void )
     /**
      * Initialise the OS before creating our threads.
      *
-     * Note that we tell the OS that the idle stack is half its actual
+     * Note that we cannot enable stack-checking on the idle thread on
-     * size. This prevents it prefilling the bottom half with known
+     * this platform because we are already using part of the idle
-     * values for stack-checkig purposes, which we cannot allow because
+     * thread's stack now as our startup stack. Prefilling for stack
-     * we are temporarily using it for our own stack. The remainder will
+     * checking would overwrite our current stack.
-     * still be available once the OS is started, this only prevents the
-     * OS from prefilling it.
      *
      * If you are not reusing the idle thread's stack during startup then
-     * you should pass in the correct size here.
+     * you are free to enable stack-checking here.
      */
-    status = atomOSInit(&idle_thread_stack[IDLE_STACK_SIZE_BYTES - 1], (IDLE_STACK_SIZE_BYTES/2));
+    status = atomOSInit(&idle_thread_stack[0], IDLE_STACK_SIZE_BYTES, FALSE);
     if (status == ATOM_OK)
     {
         /* Enable the system tick timer */
@@ -186,8 +184,9 @@ int main ( void )
         /* Create an application thread */
         status = atomThreadCreate(&main_tcb,
                      TEST_THREAD_PRIO, main_thread_func, 0,
-                     &main_thread_stack[MAIN_STACK_SIZE_BYTES - 1],
+                     &main_thread_stack[0],
-                     MAIN_STACK_SIZE_BYTES);
+                     MAIN_STACK_SIZE_BYTES,
+                     TRUE);
         if (status == ATOM_OK)
         {
             /**
@@ -246,7 +245,7 @@ static void main_thread_func (uint32_t data)
     stdout = &uart_stdout;
 
     /* Put a message out on the UART */
-    printf_P(PSTR("Go\n"));
+    printf_P (PSTR("Go\n"));
 
     /* Start test. All tests use the same start API. */
     test_status = test_start();
@@ -296,7 +295,7 @@ static void main_thread_func (uint32_t data)
         PORTB ^= (1 << 7);
 
         /* Sleep then toggle LED again */
-        atomTimerDelay(sleep_ticks);
+        atomTimerDelay (sleep_ticks);
     }
 
 }

ports/avr/uart.c

@@ -45,6 +45,8 @@
 #endif
 
 
+/* Local data */
+
 /*
  * Semaphore for single-threaded access to UART device
  */

ports/mips/.gdbinit

@@ -0,0 +1 @@
+target remote localhost:1234

ports/mips/8250-serial.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) Himanshu Chauhan 2009-11.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its 
+ *        contributors may be used to endorse or promote products derived from
+ *        this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <system.h>
+#include <atomport.h>
+#include <8250-serial.h>
+
+#define PORT1 (void *)0xc00003f8
+
+static inline unsigned int serial_in(int offset)
+{
+	return ioreadb(PORT1 + offset);
+}
+
+static inline void serial_out(int offset, int value)
+{
+	iowriteb(PORT1 + offset, value);
+}
+
+void putch(uint8_t c)
+{
+	while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
+		;
+
+	serial_out(UART_TX, c);
+}
+
+void init_console()
+{
+	serial_out(1 , 0);   /* Turn off interrupts */
+
+	/* Communication Settings */
+	serial_out(3 , 0x80);  	/* SET DLAB ON */
+	serial_out(0 , 0x01);  	/* Set Baud rate - Divisor Latch Low Byte */
+  				/*         0x03 =  38,400 BPS */
+  				/* Default 0x01 = 115,200 BPS */
+  				/*         0x02 =  57,600 BPS */
+  				/*         0x06 =  19,200 BPS */
+  				/*         0x0C =   9,600 BPS */
+  				/*         0x18 =   4,800 BPS */
+  				/*         0x30 =   2,400 BPS */
+	serial_out(1 , 0x00);  	/* Set Baud rate - Divisor Latch High Byte */
+	serial_out(3 , 0x03);  	/* 8 Bits, No Parity, 1 Stop Bit */
+	serial_out(2 , 0xC7);  	/* FIFO Control Register */
+	serial_out(4 , 0x0B);  	/* Turn on DTR, RTS, and OUT2 */
+}

ports/mips/8250-serial.h

@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) Himanshu Chauhan 2009-11.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its contributors 
+ *        may be used to endorse or promote products derived from this software
+ *        without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _8250_SERIAL_H
+#define _8250_SERIAL_H
+
+/*
+ * DLAB=0
+ */
+#define UART_RX		0	/* In:  Receive buffer */
+#define UART_TX		0	/* Out: Transmit buffer */
+
+#define UART_IER	1	/* Out: Interrupt Enable Register */
+#define UART_IER_MSI		0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI		0x01 /* Enable receiver data interrupt */
+/*
+ * Sleep mode for ST16650 and TI16750.  For the ST16650, EFR[4]=1
+ */
+#define UART_IERX_SLEEP		0x10 /* Enable sleep mode */
+
+#define UART_IIR	2	/* In:  Interrupt ID Register */
+#define UART_IIR_NO_INT		0x01 /* No interrupts pending */
+#define UART_IIR_ID		0x06 /* Mask for the interrupt ID */
+#define UART_IIR_MSI		0x00 /* Modem status interrupt */
+#define UART_IIR_THRI		0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI		0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI		0x06 /* Receiver line status interrupt */
+
+#define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */
+
+#define UART_FCR	2	/* Out: FIFO Control Register */
+#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+/*
+ * Note: The FIFO trigger levels are chip specific:
+ *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
+ * PC16550D:	 1   4   8  14		xx  xx  xx  xx
+ * TI16C550A:	 1   4   8  14          xx  xx  xx  xx
+ * TI16C550C:	 1   4   8  14          xx  xx  xx  xx
+ * ST16C550:	 1   4   8  14		xx  xx  xx  xx
+ * ST16C650:	 8  16  24  28		16   8  24  30	PORT_16650V2
+ * NS16C552:	 1   4   8  14		xx  xx  xx  xx
+ * ST16C654:	 8  16  56  60		 8  16  32  56	PORT_16654
+ * TI16C750:	 1  16  32  56		xx  xx  xx  xx	PORT_16750
+ * TI16C752:	 8  16  56  60		 8  16  32  56
+ */
+#define UART_FCR_R_TRIG_00	0x00
+#define UART_FCR_R_TRIG_01	0x40
+#define UART_FCR_R_TRIG_10	0x80
+#define UART_FCR_R_TRIG_11	0xc0
+#define UART_FCR_T_TRIG_00	0x00
+#define UART_FCR_T_TRIG_01	0x10
+#define UART_FCR_T_TRIG_10	0x20
+#define UART_FCR_T_TRIG_11	0x30
+
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+/* 16650 definitions */
+#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
+#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
+#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
+#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
+#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
+#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode (TI16C750) */
+
+#define UART_LCR	3	/* Out: Line Control Register */
+/*
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
+#define UART_LCR_SBC		0x40 /* Set break control */
+#define UART_LCR_SPAR		0x20 /* Stick parity (?) */
+#define UART_LCR_EPAR		0x10 /* Even parity select */
+#define UART_LCR_PARITY		0x08 /* Parity Enable */
+#define UART_LCR_STOP		0x04 /* Stop bits: 0=1 bit, 1=2 bits */
+#define UART_LCR_WLEN5		0x00 /* Wordlength: 5 bits */
+#define UART_LCR_WLEN6		0x01 /* Wordlength: 6 bits */
+#define UART_LCR_WLEN7		0x02 /* Wordlength: 7 bits */
+#define UART_LCR_WLEN8		0x03 /* Wordlength: 8 bits */
+
+#define UART_MCR	4	/* Out: Modem Control Register */
+#define UART_MCR_CLKSEL		0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
+#define UART_MCR_TCRTLR		0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
+#define UART_MCR_XONANY		0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
+#define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
+#define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
+#define UART_MCR_OUT2		0x08 /* Out2 complement */
+#define UART_MCR_OUT1		0x04 /* Out1 complement */
+#define UART_MCR_RTS		0x02 /* RTS complement */
+#define UART_MCR_DTR		0x01 /* DTR complement */
+
+#define UART_LSR	5	/* In:  Line Status Register */
+#define UART_LSR_TEMT		0x40 /* Transmitter empty */
+#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
+#define UART_LSR_BI		0x10 /* Break interrupt indicator */
+#define UART_LSR_FE		0x08 /* Frame error indicator */
+#define UART_LSR_PE		0x04 /* Parity error indicator */
+#define UART_LSR_OE		0x02 /* Overrun error indicator */
+#define UART_LSR_DR		0x01 /* Receiver data ready */
+#define UART_LSR_BRK_ERROR_BITS	0x1E /* BI, FE, PE, OE bits */
+
+#define UART_MSR	6	/* In:  Modem Status Register */
+#define UART_MSR_DCD		0x80 /* Data Carrier Detect */
+#define UART_MSR_RI		0x40 /* Ring Indicator */
+#define UART_MSR_DSR		0x20 /* Data Set Ready */
+#define UART_MSR_CTS		0x10 /* Clear to Send */
+#define UART_MSR_DDCD		0x08 /* Delta DCD */
+#define UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR		0x02 /* Delta DSR */
+#define UART_MSR_DCTS		0x01 /* Delta CTS */
+#define UART_MSR_ANY_DELTA	0x0F /* Any of the delta bits! */
+
+#define UART_SCR	7	/* I/O: Scratch Register */
+
+/*
+ * DLAB=1
+ */
+#define UART_DLL	0	/* Out: Divisor Latch Low */
+#define UART_DLM	1	/* Out: Divisor Latch High */
+
+/*
+ * LCR=0xBF (or DLAB=1 for 16C660)
+ */
+#define UART_EFR	2	/* I/O: Extended Features Register */
+#define UART_EFR_CTS		0x80 /* CTS flow control */
+#define UART_EFR_RTS		0x40 /* RTS flow control */
+#define UART_EFR_SCD		0x20 /* Special character detect */
+#define UART_EFR_ECB		0x10 /* Enhanced control bit */
+/*
+ * the low four bits control software flow control
+ */
+
+/*
+ * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
+ */
+#define UART_XON1	4	/* I/O: Xon character 1 */
+#define UART_XON2	5	/* I/O: Xon character 2 */
+#define UART_XOFF1	6	/* I/O: Xoff character 1 */
+#define UART_XOFF2	7	/* I/O: Xoff character 2 */
+
+/*
+ * EFR[4]=1 MCR[6]=1, TI16C752
+ */
+#define UART_TI752_TCR	6	/* I/O: transmission control register */
+#define UART_TI752_TLR	7	/* I/O: trigger level register */
+
+/*
+ * LCR=0xBF, XR16C85x
+ */
+#define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
+				 * In: Fifo count
+				 * Out: Fifo custom trigger levels */
+/*
+ * These are the definitions for the Programmable Trigger Register
+ */
+#define UART_TRG_1		0x01
+#define UART_TRG_4		0x04
+#define UART_TRG_8		0x08
+#define UART_TRG_16		0x10
+#define UART_TRG_32		0x20
+#define UART_TRG_64		0x40
+#define UART_TRG_96		0x60
+#define UART_TRG_120		0x78
+#define UART_TRG_128		0x80
+
+#define UART_FCTR	1	/* Feature Control Register */
+#define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
+#define UART_FCTR_RTS_4DELAY	0x01
+#define UART_FCTR_RTS_6DELAY	0x02
+#define UART_FCTR_RTS_8DELAY	0x03
+#define UART_FCTR_IRDA		0x04  /* IrDa data encode select */
+#define UART_FCTR_TX_INT	0x08  /* Tx interrupt type select */
+#define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
+#define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
+#define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
+#define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
+#define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
+#define UART_FCTR_RX		0x00  /* Programmable trigger mode select */
+#define UART_FCTR_TX		0x80  /* Programmable trigger mode select */
+
+/*
+ * LCR=0xBF, FCTR[6]=1
+ */
+#define UART_EMSR	7	/* Extended Mode Select Register */
+#define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
+#define UART_EMSR_ALT_COUNT	0x02  /* Alternating count select */
+
+/*
+ * The Intel XScale on-chip UARTs define these bits
+ */
+#define UART_IER_DMAE	0x80	/* DMA Requests Enable */
+#define UART_IER_UUE	0x40	/* UART Unit Enable */
+#define UART_IER_NRZE	0x20	/* NRZ coding Enable */
+#define UART_IER_RTOIE	0x10	/* Receiver Time Out Interrupt Enable */
+
+#define UART_IIR_TOD	0x08	/* Character Timeout Indication Detected */
+
+#define UART_FCR_PXAR1	0x00	/* receive FIFO threshold = 1 */
+#define UART_FCR_PXAR8	0x40	/* receive FIFO threshold = 8 */
+#define UART_FCR_PXAR16	0x80	/* receive FIFO threshold = 16 */
+#define UART_FCR_PXAR32	0xc0	/* receive FIFO threshold = 32 */
+
+
+
+
+/*
+ * These register definitions are for the 16C950
+ */
+#define UART_ASR	0x01	/* Additional Status Register */
+#define UART_RFL	0x03	/* Receiver FIFO level */
+#define UART_TFL 	0x04	/* Transmitter FIFO level */
+#define UART_ICR	0x05	/* Index Control Register */
+
+/* The 16950 ICR registers */
+#define UART_ACR	0x00	/* Additional Control Register */
+#define UART_CPR	0x01	/* Clock Prescalar Register */
+#define UART_TCR	0x02	/* Times Clock Register */
+#define UART_CKS	0x03	/* Clock Select Register */
+#define UART_TTL	0x04	/* Transmitter Interrupt Trigger Level */
+#define UART_RTL	0x05	/* Receiver Interrupt Trigger Level */
+#define UART_FCL	0x06	/* Flow Control Level Lower */
+#define UART_FCH	0x07	/* Flow Control Level Higher */
+#define UART_ID1	0x08	/* ID #1 */
+#define UART_ID2	0x09	/* ID #2 */
+#define UART_ID3	0x0A	/* ID #3 */
+#define UART_REV	0x0B	/* Revision */
+#define UART_CSR	0x0C	/* Channel Software Reset */
+#define UART_NMR	0x0D	/* Nine-bit Mode Register */
+#define UART_CTR	0xFF
+
+/*
+ * The 16C950 Additional Control Register
+ */
+#define UART_ACR_RXDIS	0x01	/* Receiver disable */
+#define UART_ACR_TXDIS	0x02	/* Transmitter disable */
+#define UART_ACR_DSRFC	0x04	/* DSR Flow Control */
+#define UART_ACR_TLENB	0x20	/* 950 trigger levels enable */
+#define UART_ACR_ICRRD	0x40	/* ICR Read enable */
+#define UART_ACR_ASREN	0x80	/* Additional status enable */
+
+
+
+/*
+ * These definitions are for the RSA-DV II/S card, from
+ *
+ * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
+ */
+
+#define UART_RSA_BASE (-8)
+
+#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
+
+#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
+#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
+#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
+#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
+
+#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
+
+#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
+#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
+#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
+#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
+#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
+
+#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
+
+#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
+#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
+#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
+#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
+#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
+#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
+#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
+#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
+
+#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
+
+#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
+
+#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
+
+#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
+
+/*
+ * The RSA DSV/II board has two fixed clock frequencies.  One is the
+ * standard rate, and the other is 8 times faster.
+ */
+#define SERIAL_RSA_BAUD_BASE (921600)
+#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
+
+/*
+ * Extra serial register definitions for the internal UARTs
+ * in TI OMAP processors.
+ */
+#define UART_OMAP_MDR1		0x08	/* Mode definition register */
+#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
+#define UART_OMAP_SCR		0x10	/* Supplementary control register */
+#define UART_OMAP_SSR		0x11	/* Supplementary status register */
+#define UART_OMAP_EBLR		0x12	/* BOF length register */
+#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
+#define UART_OMAP_MVER		0x14	/* Module version register */
+#define UART_OMAP_SYSC		0x15	/* System configuration register */
+#define UART_OMAP_SYSS		0x16	/* System status register */
+#define UART_OMAP_WER		0x17	/* Wake-up enable register */
+
+#endif /* _8250_SERIAL_H */
+

ports/mips/Makefile

@@ -0,0 +1,137 @@
+############
+# Settings #
+############
+
+# Build all test applications:
+#   make
+
+# Location of build tools and atomthreads sources
+KERNEL_DIR=../../kernel
+TESTS_DIR=../../tests
+CC=mips-linux-gnu-gcc
+OBJCOPY=mips-linux-gnu-objcopy
+
+# Check if verbosity is ON for build process
+VERBOSE_DEFAULT    := 0
+CMD_PREFIX_DEFAULT := @
+ifdef VERBOSE
+	ifeq ("$(origin VERBOSE)", "command line")
+		VB := $(VERBOSE)
+	else
+		VB := $(VERBOSE_DEFAULT)
+	endif
+else
+	VB := $(VERBOSE_DEFAULT)
+endif
+ifeq ($(VB), 1)
+	V :=
+else
+	V := $(CMD_PREFIX_DEFAULT)
+endif
+
+# Enable stack-checking. WARNING: the full automated test suite currently
+# requires a little over 1KB RAM with stack-checking enabled. If you are 
+# using a device with 1KB internal SRAM and no external SRAM then you
+# must disable stack-checking to run all of the automated tests.
+#STACK_CHECK=true
+
+# Directory for built objects
+BUILD_DIR=build
+
+# Port/application object files
+APP_OBJECTS = atomport.o tests-main.o 8250-serial.o printk.o string.o vsprintf.o io.o atomport-interrupts.o atomport-timer.o
+
+APP_ASM_OBJECTS = atomport-entry.o atomport-asm.o
+
+# Kernel object files
+KERNEL_OBJECTS = atomkernel.o atomsem.o atommutex.o atomtimer.o atomqueue.o
+
+# Collection of built objects (excluding test applications)
+ALL_OBJECTS = $(APP_ASM_OBJECTS) $(APP_OBJECTS) $(KERNEL_OBJECTS)
+BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS))
+
+# Test object files (dealt with separately as only one per application build)
+TEST_OBJECTS = $(notdir $(patsubst %.c,%.o,$(wildcard $(TESTS_DIR)/*.c)))
+
+# Target application filenames (.elf and .hex) for each test object
+TEST_ELFS = $(patsubst %.o,%.elf,$(TEST_OBJECTS))
+TEST_HEXS = $(patsubst %.o,%.hex,$(TEST_OBJECTS))
+
+# Search build/output directory for dependencies
+vpath %.o ./$(BUILD_DIR)
+vpath %.elf ./$(BUILD_DIR)
+vpath %.hex ./$(BUILD_DIR)
+
+# GCC flags
+CFLAGS= -g \
+	-Wall \
+	-Werror \
+	-O \
+	-fstrength-reduce \
+	-fomit-frame-pointer \
+	-finline-functions \
+	-nostdinc \
+	-fno-builtin \
+	-fno-stack-protector
+
+# Enable stack-checking (disable if not required)
+ifeq ($(STACK_CHECK),true)
+CFLAGS += -DATOM_STACK_CHECKING
+endif
+
+#################
+# Build targets #
+#################
+
+# All tests
+all: $(BUILD_DIR) $(TEST_HEXS) Makefile
+
+# Make build/output directory
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
+# Test HEX files (one application build for each test)
+$(TEST_HEXS): %.hex: %.elf
+	$(if $(V), @echo " (HEX)        $(subst $(build_dir)/,,$@)")
+	$(V)$(OBJCOPY) -j .text -j .data -O ihex $(BUILD_DIR)/$< $(BUILD_DIR)/$@
+
+# Test ELF files (one application build for each test)
+$(TEST_ELFS): %.elf: %.o $(APP_ASM_OBJECTS) $(KERNEL_OBJECTS) $(APP_OBJECTS)
+	$(if $(V), @echo " (ELF)        $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) $(CFLAGS) -nostdlib -nodefaultlibs $(BUILD_DIR)/$(notdir $<) $(BUILT_OBJECTS) --output $(BUILD_DIR)/$@ -Wl -T linker.ld
+
+# Kernel objects builder
+$(KERNEL_OBJECTS): %.o: $(KERNEL_DIR)/%.c
+	$(if $(V), @echo " (CC)         $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) -c $(CFLAGS) -I. -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Test objects builder
+$(TEST_OBJECTS): %.o: $(TESTS_DIR)/%.c
+	$(if $(V), @echo " (CC)         $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) -c $(CFLAGS) -I. -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Application C objects builder
+$(APP_OBJECTS): %.o: ./%.c
+	$(if $(V), @echo " (CC)         $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) -c $(CFLAGS) -I. -I$(KERNEL_DIR) -I$(TESTS_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Application asm objects builder
+$(APP_ASM_OBJECTS): %.o: ./%.s
+	$(if $(V), @echo " (AS)         $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) -c $(CFLAGS) -D__ASSEMBLY__ -x assembler-with-cpp -I. -I$(KERNEL_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# .lst file builder
+%.lst: %.c
+	$(if $(V), @echo " (LST)        $(subst $(build_dir)/,,$@)")
+	$(V)$(CC) $(CFLAGS) -I. -I$(KERNEL_DIR) -I$(TESTS_DIR) -Wa,-al $< > $@
+
+# Clean
+clean:
+	$(V)rm -f *.o *.elf *.map *.hex *.bin *.lst
+	rm -rf doxygen-kernel
+	rm -rf doxygen-mips
+	rm -rf build
+
+doxygen:
+	doxygen $(KERNEL_DIR)/Doxyfile
+	doxygen ./Doxyfile

ports/mips/README

@@ -0,0 +1,8 @@
+ * Required Ubuntu packages: qemu, qemu-kvm-extras
+   * Lucid 0.12.3 no good, better to install from source, make && sudo make install
+ * Compiler: CodeSourcery
+ * Run test: qemu-system-mips -M mips -m 128 -kernel build/kern1.elf -nographic
+
+ * GDB: Add -S -s to qemu startup
+ * mips-linux-gnu-gdb, target remote localhost:1234, file build/mutex5.elf
+ * ddd ---debugger mips-linux-gnu-gdb build/mutex5.elf

ports/mips/atomport-asm-macros.h

@@ -0,0 +1,282 @@
+#ifndef __ATOMPORT_ASM_MACROS_H_
+#define __ATOMPORT_ASM_MACROS_H_
+
+#include "regs.h"
+
+#ifdef __ASSEMBLY__ /* to be called only from assembly */
+
+#define LEAF(fn)				\
+        .globl fn;				\
+        .ent fn;				\
+fn:
+
+#define END(fn)					\
+        .size fn,.-fn;				\
+        .end fn
+
+#define tlbp_write_hazard 			\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;
+
+#define tlbp_read_hazard 			\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;
+
+#define tlbw_write_hazard 			\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;					\
+        nop;
+
+#define enable_global_interrupts		ei
+#define disable_global_interrupts		di $0
+
+#define EXCEPTION_VECTOR(_name, _offset, _where)\
+	. = _offset;				\
+	.set noreorder;				\
+_name:						\
+	b _where;				\
+	nop;
+
+#define SAVE_REG(reg, treg)			\
+        sw reg, ((reg ## _IDX) * 4)(treg)
+
+#define LOAD_REG(reg, treg)			\
+        lw reg, ((reg ## _IDX) * 4)(treg)
+
+#define SAVE_INT_CONTEXT(treg)				\
+        mfc0 k1, CP0_EPC;				\
+	SAVE_REG(t0,treg);				\
+	SAVE_REG(t1,treg);				\
+	SAVE_REG(t2,treg);				\
+	SAVE_REG(t3,treg);				\
+	SAVE_REG(t4,treg);				\
+	SAVE_REG(t5,treg);				\
+	SAVE_REG(t6,treg);				\
+	SAVE_REG(t7,treg);				\
+	SAVE_REG(t8,treg);				\
+	SAVE_REG(t9,treg);				\
+	SAVE_REG(v0,treg);				\
+	SAVE_REG(v1,treg);				\
+	SAVE_REG(a0,treg);				\
+	SAVE_REG(a1,treg);				\
+	SAVE_REG(a2,treg);				\
+	SAVE_REG(a3,treg);				\
+	SAVE_REG(s0,treg);				\
+	SAVE_REG(s1,treg);				\
+	SAVE_REG(s2,treg);				\
+	SAVE_REG(s3,treg);				\
+	SAVE_REG(s4,treg);				\
+	SAVE_REG(s5,treg);				\
+	SAVE_REG(s6,treg);				\
+	SAVE_REG(s7,treg);				\
+	SAVE_REG(gp,treg);				\
+	SAVE_REG(s8,treg);				\
+	SAVE_REG(ra,treg);				\
+        sw k0, (sp_IDX * 4)(treg);			\
+        sw k1, (cp0_epc_IDX * 4)(treg);
+
+#define RESTORE_INT_CONTEXT(treg)			\
+        lw k1, (cp0_epc_IDX * 4)(treg);			\
+        mtc0 k1, CP0_EPC;				\
+	LOAD_REG(s0,treg);				\
+	LOAD_REG(s1,treg);				\
+	LOAD_REG(s2,treg);				\
+	LOAD_REG(s3,treg);				\
+	LOAD_REG(s4,treg);				\
+	LOAD_REG(s5,treg);				\
+	LOAD_REG(s6,treg);				\
+	LOAD_REG(s7,treg);				\
+	LOAD_REG(v0,treg);				\
+	LOAD_REG(v1,treg);				\
+	LOAD_REG(a0,treg);				\
+	LOAD_REG(a1,treg);				\
+	LOAD_REG(a2,treg);				\
+	LOAD_REG(a3,treg);				\
+	LOAD_REG(t0,treg);				\
+	LOAD_REG(t1,treg);				\
+	LOAD_REG(t2,treg);				\
+	LOAD_REG(t3,treg);				\
+	LOAD_REG(t4,treg);				\
+	LOAD_REG(t5,treg);				\
+	LOAD_REG(t6,treg);				\
+	LOAD_REG(t7,treg);				\
+	LOAD_REG(t8,treg);				\
+	LOAD_REG(t9,treg);				\
+	LOAD_REG(gp,treg);				\
+	LOAD_REG(ra,treg);				\
+	LOAD_REG(s8,treg);				\
+	lw sp, (sp_IDX * 4)(treg);
+
+#endif /* __ASSEMBLY__ */
+
+#define num_to_string(s)	to_string(s)
+#define to_string(s)		#s
+
+#define IASM_SAVE_REG(reg, here)				\
+	"sw " to_string(reg) " , " num_to_string(reg ## _IDX)	\
+			     " * 4(" num_to_string(here)" )\n\t"
+
+#define IASM_LOAD_REG(reg, here)				\
+	"lw " to_string(reg) " , " num_to_string(reg ## _IDX)	\
+			     " * 4(" num_to_string(here)" )\n\t"
+
+
+/*
+ * Macros to be used with C code.
+ */
+#define __read_32bit_c0_register(source, sel)				\
+({ int __res;								\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mfc0\t%0, " #source "\n\t"			\
+			: "=r" (__res));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mfc0\t%0, " #source ", " #sel "\n\t"		\
+			".set\tmips0\n\t"				\
+			: "=r" (__res));				\
+	__res;								\
+})
+
+#define __write_32bit_c0_register(register, sel, value)			\
+do {									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mtc0\t%z0, " #register "\n\t"			\
+			: : "Jr" ((unsigned int)(value)));		\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
+			".set\tmips0"					\
+			: : "Jr" ((unsigned int)(value)));		\
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel)				\
+	(unsigned long) __read_32bit_c0_register(reg, sel)
+
+#define __write_ulong_c0_register(reg, sel, val)			\
+do {									\
+		__write_32bit_c0_register(reg, sel, val);		\
+} while (0)
+
+#define read_c0_index()		__read_32bit_c0_register($0, 0)
+#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
+
+#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
+
+#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
+
+#define read_c0_conf()		__read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context()	__read_ulong_c0_register($4, 0)
+#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
+
+#define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val)	__write_ulong_c0_register($4, 2, val)
+
+#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
+
+#define read_c0_wired()		__read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info()		__read_32bit_c0_register($7, 0)
+
+#define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
+#define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
+
+#define read_c0_count()		__read_32bit_c0_register($9, 0)
+#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
+
+#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
+
+#define read_c0_compare()	__read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
+
+#define read_c0_status()	__read_32bit_c0_register($12, 0)
+#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
+
+#define read_c0_cause()		__read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
+
+#define read_c0_epc()		__read_ulong_c0_register($14, 0)
+#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
+
+#define read_c0_prid()		__read_32bit_c0_register($15, 0)
+
+#define read_c0_config()	__read_32bit_c0_register($16, 0)
+#define read_c0_config1()	__read_32bit_c0_register($16, 1)
+#define read_c0_config2()	__read_32bit_c0_register($16, 2)
+#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
+
+#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
+#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
+
+#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val)	__write_32bit_c0_register($21, 0, val)
+
+/*
+ * MIPS32 / MIPS64 performance counters
+ */
+#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
+
+#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
+
+#define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
+#define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
+
+#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
+
+/* MIPSR2 */
+#define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
+#define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl()	__read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
+
+#endif /* __ATOMPORT_ASM_MACROS_H_ */

ports/mips/atomport-asm.s

@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2010, Atomthreads Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atomport-asm-macros.h>
+
+.section .text
+
+/**
+ * Function that performs the contextSwitch. Whether its a voluntary release
+ * of CPU by thread or a pre-emption, under both conditions this function is
+ * called. The signature is as follows:
+ *
+ * archContextSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb)
+ */
+.globl archContextSwitch
+archContextSwitch:
+    move v0, a0 /* return old tcb when we return from here */
+    lw k0, 0(a0) /* assume that sp_save_ptr is always at base of ATOM_TCB */
+    SAVE_REG(s0, k0)
+    SAVE_REG(s1, k0)
+    SAVE_REG(s2, k0)
+    SAVE_REG(s3, k0)
+    SAVE_REG(s4, k0)
+    SAVE_REG(s5, k0)
+    SAVE_REG(s6, k0)
+    SAVE_REG(s7, k0)
+    SAVE_REG(s8, k0)
+    SAVE_REG(sp, k0)
+    SAVE_REG(gp, k0)
+    SAVE_REG(ra, k0)
+
+    lw k1, 0(a1)
+    LOAD_REG(s0, k1)
+    LOAD_REG(s1, k1)
+    LOAD_REG(s2, k1)
+    LOAD_REG(s3, k1)
+    LOAD_REG(s4, k1)
+    LOAD_REG(s5, k1)
+    LOAD_REG(s6, k1)
+    LOAD_REG(s7, k1)
+    LOAD_REG(s8, k1)
+    LOAD_REG(sp, k1)
+    LOAD_REG(gp, k1)
+    LOAD_REG(ra, k1)
+
+    lw k0, (cp0_epc_IDX * 4)(k1)
+    bnez k0, 1f
+    nop
+    li k0, 0x00000001
+    sw k0, (cp0_epc_IDX * 4)(k1)
+    LOAD_REG(a0, k1)
+    LOAD_REG(a1, k1)
+    LOAD_REG(a2, k1)
+    LOAD_REG(a3, k1)
+    enable_global_interrupts
+1:
+    jr ra
+    nop
+
+/**
+ * archFirstThreadRestore(ATOM_TCB *new_tcb)
+ *
+ * This function is responsible for restoring and starting the first
+ * thread the OS runs. It expects to find the thread context exactly
+ * as it would be if a context save had previously taken place on it.
+ * The only real difference between this and the archContextSwitch()
+ * routine is that there is no previous thread for which context must
+ * be saved.
+ *
+ * The final action this function must do is to restore interrupts.
+ */
+.globl archFirstThreadRestore
+archFirstThreadRestore:
+    move k0, a0 /* save the copy of tcb pointer in k0 */
+    lw   k1, 0(k0) /* Assume that sp_save_ptr is always at base of ATOM_TCB */
+    lw   a0, (a0_IDX * 4)(k1)
+    lw   sp, (sp_IDX * 4)(k1)
+    lw   s8, (s8_IDX * 4)(k1)
+    lw   k0, (ra_IDX * 4)(k1)
+    mtc0 k0, CP0_EPC
+    nop
+    nop
+    nop
+    ehb
+    li k0, 0x00000001
+    sw k0, (cp0_epc_IDX * 4)(k1)
+    nop
+    ehb
+    enable_global_interrupts
+    ehb
+    nop
+    nop
+    eret

ports/mips/atomport-entry.s

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "atomport-asm-macros.h"
+
+.extern _stack_start
+.section .start.text,"ax",@progbits
+
+EXCEPTION_VECTOR(_tlbmiss, 0x00, _handle_tlbmiss)
+EXCEPTION_VECTOR(_cache_error, 0x100, _handle_cache_error)
+EXCEPTION_VECTOR(_general_exception, 0x180, _handle_general_exception)
+/* FIXME: We don't need this when in EIC mode. */
+EXCEPTION_VECTOR(_interrupts, 0x200, _handle_interrupt)
+
+LEAF(_start)
+	mtc0	zero, CP0_CONTEXT
+	nop
+	nop
+	nop
+
+	/* globally disable interrupts until we are prepared. */
+	disable_global_interrupts
+
+	/* clear CPU timer counters. We don't want surprises. */
+	mtc0	zero, CP0_COMPARE
+	mtc0	zero, CP0_COUNT
+
+        li      a0, 0xC0000000 /* FIXME: Remove these two hard codings */
+	li      a1, 0x14000000
+	bal     create_tlb_entry
+	move    zero, a2
+
+	la	sp, _stack_start	/* setup the stack (bss segment) */
+	la	t0, main
+	j	t0			/* Call the C- code now */
+	nop
+
+1:	b 	1b 			/* we should not come here whatsoever */
+END(_start)
+
+LEAF(_handle_tlbmiss)
+#if 0
+	disable_global_interrupts
+	move k0, sp
+	SAVE_INT_CONTEXT(_int_stack)
+	move a0, sp
+	bal vmm_cpu_handle_pagefault
+	nop
+	enable_global_interrupts
+	eret
+#else
+	b _handle_tlbmiss
+	nop
+#endif
+END(_handle_tlbmiss)
+
+.extern handle_mips_systick
+.extern _int_stack
+LEAF(_handle_interrupt)
+	disable_global_interrupts
+	mfc0 k0, CP0_CAUSE
+	lui k1, 0x4000
+	and k0, k1, k0
+	beq k0, zero, 1f
+	nop
+
+	move k0, sp
+	/* Calculate interrupt context base */
+	addi sp, sp, -(NUM_CTX_REGS * WORD_SIZE)
+	SAVE_INT_CONTEXT(sp)
+	bal handle_mips_systick
+	nop
+	RESTORE_INT_CONTEXT(sp)
+1:
+	enable_global_interrupts
+	eret
+END(_handle_interrupt)
+
+LEAF(_handle_cache_error)
+	b _handle_cache_error
+	nop
+END(_handle_cache_error)
+
+LEAF(_handle_general_exception)
+	b _handle_general_exception
+	nop
+END(_handle_general_exception)
+
+/**
+ * a0 -> Contains virtual address.
+ * a1 -> Contains physical address.
+ * a2 -> TLB index: If -1 select automatically.
+ */
+.globl create_tlb_entry
+LEAF(create_tlb_entry)
+	mtc0 a2, CP0_INDEX /* load the tlb index to be programmed. */
+	srl a0, a0, 12 /* get the VPN */
+	sll a0, a0, 12
+	nop
+	mtc0 a0, CP0_ENTRYHI /* load VPN in entry hi */
+	addi t0, a1, 0x1000 /* next PFN for entry lo1 in T0 */
+	srl a1, a1, 12 /* get the PFN */
+	sll a1, a1, 6 /* get the PFN */
+	srl t0, t0, 12
+	sll t0, t0, 6
+	ori a1, a1, 0x7 /* mark the page writable, global and valid */
+	mtc0 a1, CP0_ENTRYLO0
+	ori t0, t0, 0x7 /* mark the next physical page writable, global and valid */
+	nop
+	nop
+	mtc0 t0, CP0_ENTRYLO1
+	nop
+	nop
+	nop
+	tlbwi
+	ehb
+	j ra
+	nop
+END(create_tlb_entry)

ports/mips/atomport-interrupts.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atomport-asm-macros.h>
+#include <atomport.h>
+#include <atom.h>
+
+void mips_setup_interrupts()
+{
+        uint32_t ebase = read_c0_ebase();
+        ebase &= ~0x3FFF000UL;
+        write_c0_ebase(ebase);
+
+        uint32_t sr = read_c0_status();
+        sr &= ~(0x01UL << 22);
+        sr &= ~(0x3UL << 1);
+        write_c0_status(sr);
+
+        uint32_t cause = read_c0_status();
+        cause |= 0x01UL << 23;
+        write_c0_cause(cause);
+}
+
+void mips_enable_global_interrupts(void)
+{
+	__asm__ __volatile__ ("ei $0\t\n");
+}
+
+void mips_disable_global_interrupts(void)
+{
+	__asm__ __volatile__("di $0\t\n");
+}

ports/mips/atomport-interrupts.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOMPORT_INTERRUPTS_H
+#define __ATOMPORT_INTERRUPTS_H
+
+void mips_setup_interrupts();
+void mips_enable_global_interrupts(void);
+void mips_disable_global_interrupts(void);
+void handle_mips_systick(void);
+
+#endif /* __ATOMPORT_INTERRUPTS_H */

ports/mips/atomport-private.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2010, Atomthreads Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOMPORT_PRIVATE_H_
+#define __ATOMPORT_PRIVATE_H_
+
+/* Function prototypes */
+void mips_cpu_timer_enable(void);
+
+#endif /* __ATOMPORT_PRIVATE_H_ */

ports/mips/atomport-tests.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_PORT_TESTS_H
+#define __ATOM_PORT_TESTS_H
+
+/* Include Atomthreads kernel API */
+#include "atom.h"
+
+/* Prerequisite include for ATOMLOG() macro (via printf) */
+#include "printk.h"
+
+/* Logger macro for viewing test results */
+#define ATOMLOG printk
+#define _STR
+
+/* Default thread stack size (in bytes) */
+#define TEST_THREAD_STACK_SIZE      8192
+
+/* Uncomment to enable logging of stack usage to UART */
+/* #define TESTS_LOG_STACK_USAGE */
+
+#endif /* __ATOM_PORT_TESTS_H */
+

ports/mips/atomport-timer.c

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atomport-asm-macros.h>
+#include <atomport.h>
+#include <atom.h>
+#include <atomport-private.h>
+
+/** CPU frequency in MHz */
+#define CPU_FREQ_MHZ					100
+
+/** Number of counter counter should increase to get required ticks */
+#define COUNTER_TICK_COUNT				((1000000 * SYSTEM_TICKS_PER_SEC) / CPU_FREQ_MHZ)
+
+unsigned long long jiffies;
+
+void mips_cpu_timer_enable(void)
+{
+	uint32_t sr = read_c0_status();
+	sr |= ((0x1UL << 7) << 8);
+	write_c0_status(sr);
+
+	uint32_t cause = read_c0_cause();
+	cause &= ~(0x1UL << 27);
+	write_c0_cause(cause);
+	write_c0_compare(read_c0_count() + COUNTER_TICK_COUNT);
+}
+
+void handle_mips_systick(void)
+{
+	/* clear EXL from status */
+	uint32_t sr = read_c0_status();
+	sr &= ~0x00000002;
+	write_c0_status(sr);
+
+	/* Call the interrupt entry routine */
+	atomIntEnter();
+
+	/* Call the OS system tick handler */
+	atomTimerTick();
+
+	write_c0_compare(read_c0_count() + COUNTER_TICK_COUNT);
+
+	/* Call the interrupt exit routine */
+	atomIntExit(TRUE);
+}

ports/mips/atomport-timer.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ATOM_PORT_TIMER_H
+#define __ATOM_PORT_TIMER_H
+
+/* Required number of system ticks per second (normally 100 for 10ms tick) */
+#define SYSTEM_TICKS_PER_SEC            100
+
+void mips_cpu_timer_enable(void);
+
+#endif /* __ATOM_PORT_TIMER_H */

ports/mips/atomport.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan for Atomthreads Project.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "atom.h"
+#include "atomport-private.h"
+#include "atomport.h"
+#include "atomport-asm-macros.h"
+#include "string.h"
+
+
+/* Used for managing nesting of atomport.h critical sections */
+uint32_t at_preempt_count = 0;
+
+/**
+ * This function initialises each thread's stack during creation, before the
+ * thread is first run. New threads are scheduled in using the same
+ * context-switch function used for threads which were previously scheduled
+ * out, therefore this function should set up a stack context which looks
+ * much like a thread which has been scheduled out and had its context saved.
+ * We fill part of the stack with those registers which are involved in the
+ * context switch, including appropriate stack or register contents to cause
+ * the thread to branch to its entry point function when it is scheduled in.
+ *
+ * Interrupts should also be enabled whenever a thread is restored, hence
+ * ports may wish to explicitly include the interrupt-enable register here
+ * which will be restored when the thread is scheduled in. Other methods
+ * can be used to enable interrupts, however, without explicitly storing
+ * it in the thread's context.
+ */
+void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top,
+                            void (*entry_point)(UINT32),
+                            UINT32 entry_param)
+{
+#define STORE_VAL(base, reg, val) \
+	*((uint32_t *)(base + ((reg ## _IDX) * WORD_SIZE))) = (uint32_t)val
+
+	/* Make space for context saving */
+	uint32_t stack_start = (uint32_t)(stack_top - (WORD_SIZE * NUM_CTX_REGS));
+
+	tcb_ptr->sp_save_ptr = (void *)stack_start;
+
+	STORE_VAL(stack_start, sp, stack_start);
+	STORE_VAL(stack_start, s8, stack_start);
+	STORE_VAL(stack_start, s1, 0);
+	STORE_VAL(stack_start, s2, 0);
+	STORE_VAL(stack_start, s3, 0);
+	STORE_VAL(stack_start, s4, 0);
+	STORE_VAL(stack_start, s5, 0);
+	STORE_VAL(stack_start, s6, 0);
+	STORE_VAL(stack_start, s7, 0);
+	STORE_VAL(stack_start, cp0_epc, 0);
+	STORE_VAL(stack_start, ra, entry_point);
+	STORE_VAL(stack_start, a0, entry_param);
+}
+

ports/mips/atomport.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ATOM_PORT_H
+#define __ATOM_PORT_H
+
+
+/* Required number of system ticks per second (normally 100 for 10ms tick) */
+#define SYSTEM_TICKS_PER_SEC            100
+
+/**
+ * Definition of NULL. stddef.h not available on this platform.
+ */
+#define NULL ((void *)(0))
+
+/* Size of each stack entry / stack alignment size (32 bits on MIPS) */
+#define STACK_ALIGN_SIZE                sizeof(uint32_t)
+
+/**
+ * Architecture-specific types.
+ * Provide stdint.h style types.
+ */
+#define uint8_t   unsigned char
+#define uint16_t  unsigned short
+#define uint32_t  unsigned long
+#define uint64_t  unsigned long long
+#define int8_t    char
+#define int16_t   short
+#define int32_t   long
+#define int64_t   long long
+#define size_t    unsigned long
+#define POINTER   void *
+#define UINT32    uint32_t
+
+
+/**
+ * Critical region protection: this should disable interrupts
+ * to protect OS data structures during modification. It must
+ * allow nested calls, which means that interrupts should only
+ * be re-enabled when the outer CRITICAL_END() is reached.
+ */
+extern uint32_t at_preempt_count;
+#define CRITICAL_STORE	    uint32_t status_reg
+#define CRITICAL_START()					\
+	do {							\
+		__asm__ __volatile__("di %0\t\n"		\
+				     "ehb\t\n"			\
+				     :"=r"(status_reg));	\
+	}while(0);
+
+#define CRITICAL_END()							\
+	do {								\
+		__asm__ __volatile__("mtc0 %0, $12\t\n"			\
+				     "nop\t\n"				\
+				     "ehb\t\n"				\
+				     ::"r"(status_reg));		\
+	}while(0);
+
+/* Uncomment to enable stack-checking */
+/* #define ATOM_STACK_CHECKING */
+
+
+#endif /* __ATOM_PORT_H */

ports/mips/io.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) Himanshu Chauhan 2009-11.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *     1. Redistributions of source code must retain the above copyright notice,
+ *        this list of conditions and the following disclaimer.
+ *    
+ *     2. Redistributions in binary form must reproduce the above copyright
+ *        notice, this list of conditions and the following disclaimer in the
+ *        documentation and/or other materials provided with the distribution.
+ * 
+ *     3. Neither the name of Himanshu Chauhan nor the names of its contributors 
+ *        may be used to endorse or promote products derived from this software
+ *        without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atomport.h>
+
+uint8_t ioreadb (void *addr)
+{
+	uint8_t rv;
+	rv = *((volatile uint8_t *)addr);
+	return rv;
+}
+
+void iowriteb (void *addr, uint8_t data)
+{
+	*(volatile uint8_t *)addr = data;
+}
+

ports/mips/linker.ld

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. No personal names or organizations' names associated with the
+ *    Atomthreads project may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+OUTPUT_FORMAT("elf32-tradbigmips")
+OUTPUT_ARCH("mips")
+ENTRY(_start)
+
+SECTIONS 
+{
+	. = 0x80000000;
+	.text :
+ 	{
+		*(.start.text)
+		*(.text)
+		. = ALIGN(4);
+		_etext = .;
+	}
+
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+		_edata = .;
+	}
+
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+		_ebss = .;
+	}
+
+	.rodata :
+	{
+		*(.rodata .rodata.*)
+		. = ALIGN(4);
+		_erodata = .;
+	}
+
+	PROVIDE(_stack_end = .);
+	. = . + 8192;
+	. = ALIGN(4);
+	PROVIDE(_stack_start = .);
+	PROVIDE(_int_stack_end = .);
+	. = . + 8192;
+	. = ALIGN(4);
+	PROVIDE(_int_stack = .);
+}